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Method for package routing

IP.com Disclosure Number: IPCOM000033133D
Publication Date: 2004-Nov-29
Document File: 3 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for package routing. Benefits include improved functionality and improved performance.

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Method for package routing

Disclosed is a method for package routing. Benefits include improved functionality and improved performance.

Background

              Conventional approaches used to route differential package traces, especially flip-chip style packages, are bandwidth-limited above 2.5 Gigabits per second (Gbps). This limitation poses a potential problem for interconnects, which are expected to require transfer rates of 5 Gbps and higher.

              One of the main issues facing conventional packages is the detrimental effects of die capacitance and subsequent impedance mismatches with the interconnect on the package substrate.

              Differential bus bit-rates are increasing to higher speeds. With conventional package technology, full package characterizations (return loss and insertion loss) must be performed to ensure feasibility of the routes for high-speed differential buses. The full package characterizations are highly dependent on the routing methodology applied in the package and interaction with the die parasitics, especially die capacitance. However, the present routing methodology is not optimized for high-speed differential buses and the associated interaction with the die. Consequently, signal quality for any differential signals beyond the 2.5-Gbps bit rate is seriously degraded because of poor package performance.

              The most challenging problem with conventional packages is the routing technology. The combination of the capacitance parasitics of the analog devices on the die and the package parasitics combine to impact signal integrity. The die is connected to the package through the bumps at the die-end and with microvias, plated through holes (PTHs), and solder balls at the ball-end of the package. A capacitive circuit is created with low-impedance at the die-end. An inductive circuit with a high-impedance is created at the ball-end. The result is large mismatches in impedance at both ends, which introduce a sharp resonance frequency in the package. Large impedance discontinuities make the package full-characterization performance very poor, seriously degrading the signal integrity quality for high-speed differential buses.

              An example of the conventional routing approach is a standard 6-layer, 2-2-2 stackup flip chip package. The signal that fans-out through the breakout region near the die and is routed as a microstrip on the top or uppermost package layer . At the pin field it is then connected through a microvia and PTH via to the bottom layer where it is connected to the ball with very minimal trace routing on the bottom layer. The on-die capacitance at the die-end acts as a capacitive circuit and the microvia, PTH via, and ball at the ball-end act as an inductive circuit. Both mismatches limit the package performance by sharpening the resonance frequency of the package.

              In summary, major issues exist with the conventional routing technology:

1.           Very high miss-match impedanc...