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Array Cap with Multiple Voltage Rails Matching Silicon Layout

IP.com Disclosure Number: IPCOM000033138D
Publication Date: 2004-Nov-29
Document File: 2 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that partitions the planes within an array cap to allow for multiple voltage rails. Benefits include replacing multiple discrete caps with a single array cap that provides better performance and lower series inductance.

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Array Cap with Multiple Voltage Rails Matching Silicon Layout

Disclosed is a method that partitions the planes within an array cap to allow for multiple voltage rails. Benefits include replacing multiple discrete caps with a single array cap that provides better performance and lower series inductance.

Background

A standard array cap typically consists of several pairs of alternating power and ground planes inside a ceramic-based substrate. These planes act as several parallel plate capacitors that produce a high capacitance. The array cap also has several power and ground vias connecting the planes together; each one of these vias ends in a capacitor terminal. Having a large number of terminals helps reduce the ESL of the array cap. The array cap is typically assembled on the land side of the substrate under the die shadow. Figure 1 shows the cross-section of a typical array cap.

There is a need to decouple multiple voltage rails within a single array capacitor element. Currently, this is handled by using multiple discrete caps. 

General Description

In the disclosed method, the power planes in the array cap are partitioned to mimic the distribution of the power rails on the die. The ground plane is shared between all the different power rails, and as a result, the ground plane on the array cap is not partitioned. Figure 2 shows the distribution of the power rails in the die, while Figures 3 and 4 show how the power and ground planes in the array cap are designed for that d...