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Stacked Semiconductor Package Crack Mitigation

IP.com Disclosure Number: IPCOM000033146D
Publication Date: 2004-Nov-29
Document File: 2 page(s) / 7M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that deposits a coating material onto all exposed semiconductor chips and substrate surfaces contained within a stack of semiconductors. Benefits include reducing the cracks associated with thermo-mechanical stresses.

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Stacked Semiconductor Package Crack Mitigation

Disclosed is a method that deposits a coating material onto all exposed semiconductor chips and substrate surfaces contained within a stack of semiconductors. Benefits include reducing the cracks associated with thermo-mechanical stresses.

Background

Temperature cycling and thermal stressing may cause cracks in the corner of a semiconductor; these cracks can extend along and through the edges of the semiconductor device. Cracks or separations can also extend along the interface between the semiconductor device and the mold compound encapsulant. When the cracks in the semiconductor device become large enough, the semiconductor fails electrically.

General Description

The disclosed method deposits a coating material onto all exposed semiconductor chips and substrate surfaces contained within a stack of semiconductors. The coating material adheres to both the exposed surfaces of the semiconductors and substrate, as well as the molding compound used to encapsulate the final package. The coating material is also applied thick enough so that the inherent syntactic physical properties (such as elongation and modulus) provide a “slip-plane” or “stress relief plane” within the coating to allow it to flex, and mitigate any thermo-mechanical stress within the package. The coating can be applied to individual packages, or to multiple packages produced together in an array or checkerboard fashion prior to singulation. Figures 1 throug...