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Kerf design and process interaction to improve chip defect density

IP.com Disclosure Number: IPCOM000033328D
Original Publication Date: 2004-Dec-07
Included in the Prior Art Database: 2004-Dec-07
Document File: 2 page(s) / 93K

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The removal and suppression of defects is critical for achieving the yield requirements of 0.13um embedded DRAM (eDRAM) products. During the formation of the deep trench (DT) capacitors, non-ideal lithography and etching cause fragile pillars to form on the edge of the wafer. These pillars are easily broken off during subsequent processing and become defects on the surface of the wafer. The remaining pillars on the edge and the bevel of the wafer also trap surface fm during subsequent processing. Disclosed is a process whereby adjusting the kerf DT fill pattern density, the printing of pillars is suppressed, and the generation of defects due to this mechanism is eliminated.

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Kerf design and process interaction to improve chip defect density

The fabrication of eDRAM technology requires a multi-step process to form the DT capacitors, prior to the start of the standard CMOS process flow. Since defects are already prohibitive for limiting yield on the standard CMOS products, additional defects generated by the DT processing should be minimized. There are different types of defects generated during the DT processing, and one such type is silicon chards. Silicon chards are generated on the edge of the wafer due to non-ideal lithography conditions. Due to the curvature of the wafer and the presence of thicker resist, the DTs on the edge of the wafer are printed as pillars for a certain critical pattern density of DT on the mask. Higher pattern density DTs are more likely to print as pillars versus lower pattern density DTs. The pillars that form from the DT etch are very fragile due to their high aspect ratio. It has been observed that during subsequent processing, the pillars are susceptible to breakage, causing large numbers of defects to populate the wafer surface. One very strong interaction of a downstream process and pillar breakage is the process used to remove resist in the trenches following the resist recess etch that defines the buried plate. This process is run in a tool that sprays chemicals starting from the edge of the wafer. It has been observed that this process also breaks and sprays silicon pillars across the wafer. The result of this effect is shown in figure 1.

Figure 1. Wafer map showing spray...