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Automated Test Equipment Memory On-Demand

IP.com Disclosure Number: IPCOM000033329D
Original Publication Date: 2004-Dec-07
Included in the Prior Art Database: 2004-Dec-07
Document File: 7 page(s) / 39K

Publishing Venue

IBM

Abstract

The Automated Test Equipment (ATE) pattern memory required to test an Integrated Circuit (IC) continues to grow, with the most advanced and complex IC's requiring significantly more pattern memory than others. In order for manufacturers and test houses to have the flexibility to test any IC anywhere on their test floor, each ATE station must have enough additional pattern memory to test the more complex IC's that require it. Because relatively few IC's require this additional pattern memory, the additional pattern memory remains idle on the majority of ATE stations that are not using it. This idle memory is a waste of resources and can be eliminated by dynamically allocating additional ATE pattern memory from a RAM Server via a Dense Wavelength Division Multiplexing (DWDM) Fiber Optic (FO) Network.

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Automated Test Equipment Memory On -Demand

Introduction

All IC's have Input and Output (IO) circuitry that can be used to communicate with an ATE station (ATE configured for mass production). ATE stations use these IO to test the internal structure of the IC's (are all of the internal nets intact?), the functional behavior of the IC's (does the IC behave externally as expected?), or both.

Testing an IC requires the application of stimulus by an ATE station, followed by the comparison of the IC response to a known value. For internal structural and external functional testing, each application of stimulus and expected response, through an IO, is referred to as a test vector. A sequence of test vectors is referred to as a test pattern. Patterns of vectors for structural and functional testing are contained within ATE pattern memory.

Structural testing requires very few IO to test an IC, but the number of vectors may be very high
(i.e., the length of the patterns may be very long). The stimulus can be loaded into the IC through a single IO, as a long and narrow chain of stimuli, setting all of the internal nets to a known state. Next, the IC is clocked by the ATE station, exercising the internal structures. Finally, the IC response can be unloaded as a long and narrow chain of data and compared to the expected responses by the ATE station. Multiple vector chains can be loaded and unloaded through multiple IO, simultaneously, to reduce the amount of time spent loading and unloading the IC. These long chains of vectors are often referred to as scan chains, and some ATE have dedicated memory for storing these vectors, called ATE Scan Vector Memory (SVM).

Functional testing may use all of the IO available to test an IC, with the ATE station emulating an external device that the IC must communicate with, verifying that the IC will function as expected in its final application and/or operating environment. In this scenario, each stimulus and expected response (i.e., vector) is applied to all of the required IO in parallel. Again, a sequence of vectors is referred to as a pattern, and the ATE pattern memory used to store these vectors is referred to as ATE Parallel Vector Memory (PVM).

SVM is usually dynamically configurable, meaning the number of test IO channels in the SVM can be increased at the expense of the number of vectors that can be stored. For example, a typical ATE station with 8G of SVM can apply 8G vectors to a single IO, 4G vectors to two IO, 2G vectors to four IO, etc. If this algorithm were extended to 512 IO channels, the 8G of SVM would look like 16M of PVM, but possibly with some performance limitations. However, most SVM cannot be configured to apply vectors to more than 64 IO channels, so PVM is required for functional testing.

PVM is dedicated to the test IO channels of an ATE station and cannot be dynamically allocated to other test IO channels. A typical ATE station with 16M of PVM can apply 16M vectors to each IO....