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Improved RAS in PCI, PCI-X and PCI-Express based systems -- particularly LPARed systems -- by prevention of peer to peer operations via a bit in the switch or bridge configuration space

IP.com Disclosure Number: IPCOM000033443D
Original Publication Date: 2004-Dec-10
Included in the Prior Art Database: 2004-Dec-10
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Abstract

This article discusses methods of detecting and preventing peer-to-peer operations between peer I/O Adapters (IOAs) in PCI, PCI-X, and PCI Express based systems.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 42% of the total text.

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Improved RAS in PCI, PCI-X and PCI-Express based systems -- particularly LPARed systems -- by prevention of peer to peer operations via a bit in the switch or bridge configuration space

Disclosed are enhancements to PCI, PCI-X, and PCI Express* based systems to detect and prevent peer-to-peer operations between peer I/O adapters (IOAs) in order to improve the Reliability, Availability, and Serviceability (RAS) characteristics of these systems. This article assumes basic working knowledge of the PCI, PCI-X, and PCI Express standards. The enhancements described by this article are optional and may be turned on and off via configuration space bits in a parent switch or bridge.

Legend

Figure. Typical PCI Switch/Bridge with Enhancements

MRR 0

GNT

LB 0

ARB

Shared Bus/DEVSEL

BAR 1

MRR 0

BAR 2

MRR 0

BAR 3

MRR 0

LB 1

LB 2

LB 3

Upstream Port Downstream Port

LB = Logical Bridge

IOA = I/O Adapter

BAR = Base Address Registers

MRR = Memory Range Registers

ARB = Bus Arbiter

GNT = Grant Line to LB 0

Memory Range Register Replication Enhancement

Grant Line Replication Enhancement

IOA 1

IOA 2

IOA 3

Typically, PCI, PCI-X, and PCI Express switches/bridges consist of several PCI-to-PCI bridges (either logical or physical) connected via a shared internal bus. In some implementations, the internal bus of these types of switches/bridges may be implemented by a PCI-X bus or something similar (see Figure ignoring enhancements). In such a case, a DEVSEL signal indicates if a device is responding to an address broadcast upon the shared internal bus. A device asserts the shared DEVSEL signal if the address broadcast upon the shared internal bus falls within the range of its Base Address Registers. For example, if IOA 2 in Figure broadcasts an address that falls within the address range that BAR 1 specifies, LB 1 will assert the DEVSEL signal on behalf of IOA 1 and IOA 1 will execute the command requested by IOA 2 on a subsequent cycle. This is an example of a peer-to-peer operation since IOA 1 and IOA 2 are both within the address space of the switch/bridge. In order to prevent unintentional peer-to-peer operations and peer-to-peer operations between IOAs not controlled by the same operating system (OS) image, these peer-to-peer operations must be prevented. The current PCI, PCI-X, and PCI Express standards do not contain an architected method to prevent peer-to-peer operations.

The disclosed adds a Peer-to-Peer Disable bit within the configuration registers of PCI, PCI-X, and PCI-Express devices' (such as LB 1, LB 2, and LB 3 in Figure) downstream ports. In order to support legacy PCI device implementations, this bit may reside in one

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the reserved bit positions of the Bridge Control Register. Call this bit the Peer-to-Peer Disable Bit. When this bit is a one for a switch/bridge downstream port, devices on this port must only communicate with other devices outside of the address space of the switch/bridge to which this device is attached (that i...