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A Method to Allow an Infinite Number of PCI ROMs to Execute in a Constrained Memory Environment

IP.com Disclosure Number: IPCOM000033490D
Original Publication Date: 2004-Dec-13
Included in the Prior Art Database: 2004-Dec-13
Document File: 6 page(s) / 43K

Publishing Venue

IBM

Abstract

On current xSeries servers, current PCI specification and chipset technology requires that all PCI/PCI-X/PCI express ROMs reside and execute in the 0xC000-0xD000 memory segments. When this limit is exceeded, the system POST/BIOS firmware will generate a "1801 PCI Error" indicating that all ROM space has been exhausted, and subsequent devices in the boot sequence may or may not function. As seen on scalable systems such as the x445, a system may have as many as 48 slots (8 way partition with two RXE expansion units), which will easily exceed the 128 KB available memory in most configurations. This problem is forcing the customer to tailor the system to their configuration, disabling unused devices and/or defining a strict boot order based on installed adapters. What is needed is a method to allow an unlimited amount of PCI device ROMs to execute while not forcing the end user to modify the system configuration.

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A Method to Allow an Infinite Number of PCI ROMs to Execute in a Constrained Memory Environment

    The basic idea is to intercept each device before and after he has ROM execution and store his data in a different area giving 128K total for each device.

    The benefit of the solution would allow ANY device to use the maximum 128K area with out affecting other devices and remove any 1801 error. This will allow us to have an unlimited number of ROM devices, since each device has the total 128K area. This would also allow us to sale more adapter because we would not have the limitation and allow more flexibility of our customers.

     Figure 1: Flowchart for POST/BIOS PCI Device Initialization and ROM Execution Procedure:

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 POST/BIOS PCI device initialization begins

Save current interrupt vector table values to determine if device will hook interrupt(s)

More PCI devices to initialize?

No

Yes

Configure PCI device resources as needed

(IO, memory, interrupt)

No

 Was at least 1 C000:D000 page full/changed out?

Yes

Does device have option ROM?

Replace changed vectors with new ROM paging handlers

No

Yes

Yes

Will ROM fit in current C000:D000 space?

End of PCI device initialization

No

Copy current device's ROM to C000-D000 segment

 Replaced each changed interrupt vectors with a new ROM paging handler vector, but save the old vector entry address

  Copy current C000:D000 memory contents to upper memory for storage (reserved by BIOS in E820)

Copy current device's ROM to C000:D000 segments

Run PCI ROM

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Copy current device's ROM to C000:D000 segments

Run PCI ROM

Figure 2: Flowchart for ROM Paging Interrupt Handler

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 Int X is called or physical hardware interrupt line is asserted

POST/BIOS ROM paging handler is invoked

Is original vector to be called in C000:D000 region?

No

 Save the current C000:D000 segment contents in memory

Yes

Fill the C000:D000 segments with the appropriate saved page

Interrupt vector (ex int 13h) runs in C000:D000 segments and then returns back to ROM paging handler

Was C000:D000 copied in?

Yes

No

ROM paging handler copies C000-D000 back to reserved memory and copies in original page

ROM pag...