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Rapid Extraction of Electrical Parasitics for Interconnect Wires on Semiconductor Chips

IP.com Disclosure Number: IPCOM000033527D
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
Document File: 3 page(s) / 22K

Publishing Venue

IBM

Abstract

A fast and efficient extraction solution of general full chip global wiring of gridless wires using two dimensional lateral searches. The technique reduces runtime with a minor accuracy tradeoff.

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Rapid Extraction of Electrical Parasitics for Interconnect Wires on Semiconductor Chips

This publication describes a new solution to the problem of fast and efficient extraction of general full chip global wiring.

The new program is an extension of US Patent 6185722 issued 02/06/2001 "Three dimensional track-based parasitic extraction".

The Characteristics of US Patent 6185722 are a restriction of wires to a uniform grid and a predefined set of wire types, which can have different width with a set grid-overhang. Also a three dimensional byte map encodes the presence of metal at all grid-points. This setup enables the use pre computed 3 dimensional capacitance values in relative small tables. The effect is a small accuracy tradeoff yielding a very fast extraction methodology.

The current publication extends this concept into a gridless environment, allowing any wire width and space, taking advantage of several other ideas. It maintains the approximations defining global wire interconnect in contrast to local transistor connects.

The basis of the 2 dimensional lateral searches of wires and wire environment on the same level is the similar as in the program described above. A two dimensional byte map encoding the presence of metal within a grid based on the minimum wire width and space possible on this level within the technology capabilities. The code recognized the width of the wire and follow the perimeter measuring the space to the next closest wire, and the length of the common distance. It calculates the capacitance of a segment as an area capacitance and an edge capacitance using the area measurements and edge length and space measurements. This type of search is disclosed in US05761080 issued 06/02/1998 "Method and apparatus for modeling capacitance in an integrated circuit."

The biggest problem for this type of capacitance extraction lays in the large number of changing geometries due to crossing wires in the layers above and underneath. To remove the complexities from this situation, the new code uses a modification of the method described in US 6 574 782 B1 of Jun.3, 2003: "Decoupled Capacitance Calculator for Orthogonal Wiring Patterns".

This invention calculates out of the pattern densities and dielectric distances above and below an effective dielectric distance to a single virtual wiring plate above and below. In this way the effect of the varying dielectric distance above and below is averaged so that the total capacitance of a wire segment is maintained. The effective distance of this plate is pre-calculated for density segments of some 100 wire tracks. The code in this patent uses this effective distance for the area capacitance and a three dimensional function for the edge capacitance.

The code described here does not use an effective distance to a virtual plane, but breaks the area in a density block up in a region equivalent to a capacitance to the level directly above, an area equivalent to the cap to two levels...