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A method for enhancing the manufacturability and signal integrity of VLSI designs.

IP.com Disclosure Number: IPCOM000033532D
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Abstract

We present a method for enhancing the manufacturability and reliability of vias in a VLSI layout by adding redundant vias and metal borders.

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A method for enhancing the manufacturability and signal integrity of VLSI designs .

Disclosed is a method for automatically enhancing an existing ground-rule correct physical design in a circuit and net-aware manner. The particular embodiment we describe pertains to the connections between vias and metal layers, although the technique described is applicable to a wide range of physical design rules and electrical characteristics.

Even though a very large-scale integrated-circuit (VLSI) design may be correct with respect to the design rules for a given manufacturing technology, it is frequently desirable to modify the physical design to increase its manufacturability or to improve its electrical characteristics. One of the most common modifications is to enforce so-called recommended ground rules: spacing and width tolerances that are greater than the minimum ground-rule values described by the technology design rules.

If a circuit or design has not yet been laid out, these recommended ground rules can be used during the physical-design phase. But for an existing physical design, the manual modification of a design to obey recommended values instead of minimum values can be tedious and even intractable. We present a technique for automatically modifying and existing physical design to enforce recommended ground rules.

The method consists of four main parts.

(1) Identification of sensitive vias. Sensitive vias can be chosen based on some geometric or electrical characteristic. Vias that are particularly sensitive to electrical degradation are the vias that connect to the outputs of circuit elements, since any increased resistance in such a via will affect the alternating-current (AC) performance--perhaps in a manner that may result in not satisfying the AC performance target, but still allowing direct-current (DC) connectivity. This may result in test escapes unless AC test is performed. Geometrical identification can be made using a shapes-processing program. Identification based on electrical characteristics can be made by marking the shape in the design database with an attribute from the schematic for the circuit.

Once the target vias are identified, a marker shape is placed around the vias using the shapes-processing program.

(2) Addition of redundant vias wherever possible. A standard redundant-via tool (see, for example, US Patent 6,026,224) can be used to add a redundant vias whenever possible to each of the target vias. The marker shape from (1) is removed from those vias for which a redundant vias can be added.

(3) Enforcement of recommended ground rules for vias for which a redundant via could...