Browse Prior Art Database

Programmable Single Cycle Imager Interface

IP.com Disclosure Number: IPCOM000033539D
Original Publication Date: 2004-Dec-15
Included in the Prior Art Database: 2004-Dec-15
Document File: 3 page(s) / 66K

Publishing Venue

Motorola

Related People

L. Dawson: AUTHOR [+2]

Abstract

The purpose of this design was to provide a flexible, single-cycle image sensor interface that could generate/receive controls signals to/from various sensors and receive sensor image data

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Programmable Single Cycle Imager Interface

L. Dawson and J. Crenshaw

Embedded Systems and

Physical

Science

Center

of Excellence, Motorola Labs

Abstract

The purpose of this design was to provide a flexible, single-cycle image sensor interface that could generate/receive controls signals to/from various sensors and receive sensor image data.

Body

A variety of Image Sensor Interfaces exist, all of which require single cycle response time. The interfaces utilize various combinations and polarities of horizontal synchronization, vertical synchronization, frame valid and field signals. In Figure 1 examples of row and frame timing are shown for two possible signal combinations, one utilizing hsync and vsync and one utilizing hsync and frame valid. To communicate with a variety of sensors a flexible interface at the image processor is required. In addition, advanced features such as windows of interest, selection of a window of pixels in a frame, and decimation, removing pixels at regular intervals, are often desired.

Figure 1 Examples of Possible Sensor Interface Timing

The purpose of this design was to provide a flexible, single-cycle image sensor interface that could generate/receive controls signals to/from various sensors and receive sensor image data. The single cycle operation is critical to allow the interface to operate at the same frequency as the image sensor to reduce power consumption and design complexity. The design is based on a flexible RAM based state machine with counters, is application programmable and can interface to a variety of sensors. The programmability allows implementation of the desired windows of interest and decimation. Figure 2 is a block diagram of the design implemented in Motorola’s AVEC_lite IC.

Figure 2 SIF Block Diagram

The state machine consists of a state RAM, which contains the current state, an output RAM, which...