Browse Prior Art Database

Inline Device Structure and Method for Evaluating Negative Bias Temperature Instability (NBTI) for Silicon-On-Insulator (SOI)

IP.com Disclosure Number: IPCOM000033546D
Original Publication Date: 2004-Dec-16
Included in the Prior Art Database: 2004-Dec-16
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Abstract

In advanced semiconductor technologies, Negative Bias Temperature Instability (NBTI) is becoming the main degradation mechanism of concern. The invention proposed in this article uses heating in the silicon body of Silicon-on-Insulator (SOI) devices to heat the channel area of P-MOSFETs to an appropriate level to generate measurable NBTI degradation. This is important to develop in-line tests that can monitor NBTI quickly and efficiently. The method of heating the silicon body is by using transistors which share the same silicon body with the device under test (DUT) to heat the silicon body by self-heating effects. Other methods of heating (such as using silicides on the silicon body as resistive heaters) may be used to similarly raise the local temperature in the silicon.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Inline Device Structure and Method for Evaluating Negative Bias Temperature Instability (NBTI) for Silicon-On-Insulator (SOI)

NBTI is a well known degradation mechanism of P-MOSFETs [1], although the physics is not well understood [2]. NBTI occurs when the voltage applied to the gate of the P-MOSFET device (the DUT) is low (negative) with respect to the source, drain and n-well. Furthermore, NBTI is exacerbated at high temperatures and long times. The damage caused by NBTI can be measured by evaluating the electrical parameters of the DUT, such as the threshold voltage shift (∆Vt) or the drain current degradation (∆Id). In some applications where NBTI is to be measured (such as an in-line monitoring test in a manufacturing environment), it is advantageous to keep testing times short and the wafer temperatures low - typically room temperature. Furthermore, there is a limit to the amount of voltage that can be applied to the gate due to the dielectric breakdown of the gate oxide. Thus, raising the local temperature of the device using an external power supply is necessary to quickly generate measureable NBTI shifts.

The structure and method described in this article provides for a stable, reliable heating of the DUT using the self-heating of one or more transistor devices which share the same silicon body as the DUT. For example, Fig. 1 shows two heating devices (defined by Gates 1 and 3) on either side of the DUT (defined by Gate 2.) Other methods to heat the same silicon body as the DUT can also be used, such as using the silicide on the silicon body to act as a resistive heater. This publication shall refer to Fig. 1 for the purposes of this article, but the method described is easily adapted for other heating elements.

Figure 1

The structure described above differs from other published structures in that it uses the silicon body of the DUT to transmit heat from the heating element to the DUT. Other disclosures use resistive poly heaters to generate high temperatures[3], or infer the NBTI degradation from other degradation mechanisms[4]. The structure in this disclosure can be made with existing mask levels and processes. The heating devices in Fig. 1 can be optimized to give the most efficient heating. Also note that in the configuration shown in Figure 1, the heating devices can double as hot-carrier

1

[This page contains 1 picture or other non-text object]

Page 2 of 3

monitors. The DUT can be used as a hot-carrier monitor after the NBTI stress in order to minimize the NBTI influence on the hot-carrier damage. The external voltages and times used in this structure and methodology depend upon the technology definition and should be predetermined for the inline test.

The general method of using this structure to monitor NBTI is as follows: (1) The DUT

(defined by Gate 2) is characterized before the NBTI stress. (2) Nodes 2 and 3 are grounded and Nodes 1 and 4 are held at a voltage appropriate for the technology being measured...