Browse Prior Art Database

FET device with a gate conductor width larger than the minimum dimension by a sub-grid dimension

IP.com Disclosure Number: IPCOM000033582D
Original Publication Date: 2004-Dec-16
Included in the Prior Art Database: 2004-Dec-16
Document File: 6 page(s) / 533K

Publishing Venue

IBM

Abstract

The methods described in this publication provides the solution to the problem encountered in the conventional lithography as well as in the edge imaging techniques such as SIT (Sidewall Image Transfer) and phase edge lithography. In conventional lithography, mask dimension cannot be changed continuously, but only be able to change incrementally by a grid dimension. Often, a device with channel length longer by less than the dimension produced by one grid mask dimension is desirable. For example, minimum dimension NFETs and slightly longer PFETs in SRAM provide high performance with more robust operation and thus higher test yield.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 6

FET device with a gate conductor width larger than the minimum dimension by a sub-grid dimension

Process to form a gate conductor width larger than the minimum dimension by a sub-grid dimension

Problems solved by this invention

In conventional lithography, mask dimension cannot be changed continuously, but only changed incrementally by a grid dimension. Often, a device with channel length longer by less than the dimension produced by one grid is desirable. For example, minimum dimension NFETs and slightly longer PFETs in SRAM

By SIT (or other sub-lithograhic edge imaging techniques), a sub-lithographic image of only one dimension is created.

Often, a device with a slightly longer channel length is desirable.

For example, minimum dimension NFETs and slightly longer PFETs.

Process steps prior to the figure 1

0.0. p type Si substrate.
0.1. Device isolation (STI) formation by etching Si substrate, filling the trench by CVD oxide followed by planarization by CMP
0.2. Well (P-well and N-well) formation by ion implantation with blocking mask
0.3. Gate dielectric formation (thermal oxide or thermal oxynitride, plasma nitridized thermal oxide, or CVD oxynitride or high-k materials)
0.4. Patterning of PolySi -polySi deposition, photolithography and etching of polySi followed by photo resist strip

PC etch Leaving about 10nm polySi uneteched

NFET PFET

1

[This page contains 1 picture or other non-text object]

Page 2 of 6

Oxide spacer formation of dimension smaller than the gr...