Browse Prior Art Database

Multi Chip Mask Die Rotation & Mirror to Minimize Lens Exposure Aberrations on Chip Performance

IP.com Disclosure Number: IPCOM000033671D
Original Publication Date: 2004-Dec-22
Included in the Prior Art Database: 2004-Dec-22
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Abstract

Integrated Circuit (IC) chip characteristics (ex: speed, performance, timing, etc.) vary based on the optical distortion of stepping imaging systems and semiconductor processes used in the wafer manufacturing line. This generally takes on the form of radial distortion, causing differences based on distance from center of the lens and/or wafer. Current wafer manufacturing methods employ identical orientation of chips on a wafer (and multi chip reticles / masks). This has a disadvantage when multi-chip reticles are employed, because lens distortion and manufacturing processes are known to effect each chip within the reticle differently. This manifests itself as a lack of consistency between identical x,y locations on a chip. For example, a four chip reticle produces four uniquely performing chips. It is an advantage for all manufactured chips to perform identically. This invention will describe a means to achieve better consistency with currently available lenses and processes.

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Multi Chip Mask Die Rotation & Mirror to Minimize Lens Exposure Aberrations on Chip Performance

Title: Multi Chip Mask Die Rotation & Mirror to minimize lens exposure aberrations on chip performance Lead: Tad Wilder

BACKGROUND

Integrated Circuit (IC) chip characteristics (ex: speed, performance, timing, etc.) vary based on the optical distortion of stepping imaging systems and semiconductor processes used in the wafer manufacturing line. This generally takes on the form of radial distortion, causing differences based on distance from center of the lens and/or wafer.

Current wafer manufacturing methods employ identical orientation of chips on a wafer (and multi chip reticles / masks). This has a disadvantage when multi-chip reticles are employed, because lens distortion and wafer manufacturing processes are known to effect each chip within the reticle differently. This manifests itself as a lack of consistency between identical x,y locations on a chip. For example, a four chip reticle produces four uniquely performing chips. It is an advantage for all manufactured chips to perform identically.

This invention will describe a means to achieve better consistency with currently available lenses and processes.

PRIOR ART

Searches in Delphion and IEEE have not highlighted any patents or publications covering this invention. The board highlighted early hardware, shared mask between multiple chip designs, in which area use is maximized potentially via differenct product chip rotation. This approach intent is still different from the current art being done; in particular the rotate and mirror embodiment described below.

Much work has been done in IC wafer stepper lens characterization, understanding, impacts, improvement, etc. Two IEEE papers are cited, as follows: (1) Krivokapic, Z., et al., "Intrafield Effects on Device and Circuit Manufacturability: A Statistical Simulation Approach", IEEE Transactions on Semiconductor Manufacturing, Vol. 12, No. 4 (Nov. 1999), pp. 437-451; and (2) Monahan, J., et al., "Yield Impact of Cross-Field and Cross-Wafer CD Spatial Uniformity: Collapse of the Deep-UV and 193nm, Lithographic Focus Window,", 0-7803-5403 (June 1999), pp. 115-118.

INVENTION SUMMARY

This invention consists of rotation and/or mirroring of the chips within a multi-chip reticle to achieve consistency across chips. With this consistency, optimal orientation can be selected to maximize performance based on desired circuit characteristics: Speed, Power, etc.

INVENTION DETAILS

The following drawings show four unique invention embodiments:
1) Square chip rotation within a multi-chip reticle
2) Square chip mirror and rotation within a multi-chip reticle 3a) Rectangular chip rotation within a multi-chip reticle 3b) Rectangular chip mirror and rotation within a multi-chip reticle

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BAU layout for a 4-chip reticle

BAU layout for a 4-chip reticle

Stepper Lens Induced Variations

mask

mask

BAU Problems w/ 4-chip reticle

(CU08 wafer test re...