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High Vcc SRAM Array for Read Stability Improvement

IP.com Disclosure Number: IPCOM000033782D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 163K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve SRAM cell read stability without increasing the cell area or requiring a negative supply voltage. Benefits include maintaining device reliability limits.

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High Vcc SRAM Array for Read Stability Improvement

Disclosed is a method to improve SRAM cell read stability without increasing the cell area or requiring a negative supply voltage. Benefits include maintaining device reliability limits.

Background

With the scaling of transistor dimensions, variability in the number and location of channel dopont atoms results in deviations in the device threshold voltage. These fluctuations are most prominent in minimum geometry devices commonly used in area-limited circuits (see Figure 1). The mismatch of threshold voltages between neighboring devices within an SRAM cell can dramatically reduce cell stability during a read operation.

Read stability is when a cell flips its content during a read operation while considering device mismatch. Cells are most susceptible to noise during a read operation, because as the selected word-line (WL) starts rising, the voltage divider along the access and the pull-down transistors (Ma1 and Mn1) cause the low storage node (C0) to rise above “0”, the lower the resistance of Mn1 relative to that of Ma1, the smaller the noise on the “0” node. The lower this noise figure, the more stable the cell is. However, process scaling will make it harder to meet this requirement, since device parameter variations will continue to increase.

Currently, cell stability can be improved by:

§         Increasing the width of the pull-down NMOS which results in larger cell areas and makes the cell harder to write.

§         Increasing the channel length of the access transistor which results in a slower read cell speed.

§         Increasing the strength of the pull-down NMOS device by driving its source terminal to a negative voltage just before WL is turned on. This boosts the drive of the pull-down NMOS by increasing both the gate-to-source and the drain-to-source voltages. This method requires a scalable negative supply voltage generator with associated area, power, and tracking overheads.

General Description

The disclosed method improves SRAM cell read stability without increasing the cell area or requiring a negative supply voltage. The disclosed method operates the SRAM array at a high Vcc (HVcc), independent of the surrounding blocks (i.e. other logic on the same chip). Since neighboring logic can operate at HVcc or a lower Vcc (LVcc), a level-up shifter is used at the SRAM array interface to guarantee the proper signal translation between the two domains. (s...