Browse Prior Art Database

Automatic Flow for the Accurate Computation of Resistances in the VLSI Layout

IP.com Disclosure Number: IPCOM000033783D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 117K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that computes pin-to-pin resistance between pin pairs, making sure parasitic extraction, timing, and noise are accurate, and that other applications receive the resistance information.

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Automatic Flow for the Accurate Computation of Resistances in the VLSI Layout

Disclosed is a method that computes pin-to-pin resistance between pin pairs, making sure parasitic extraction, timing, and noise are accurate, and that other applications receive the resistance information.

Background

With today’s very narrow line widths, accurate resistance values are critical to the correctness and convergence of a design. However, designers are not computing the resistance of non-trivial paths because of the labor involved; this may lead to over designing, or to not achieving the target frequency.

Currently, interconnection polygons are not sent to computation as a single entity, but are fractured into linear and non-linear regions. This fracturing makes the resistance computation inefficient due to the multitude of regions sent to computation. It also makes the computation less accurate since the total pin-to-pin resistance is computed as the algebraic sum of the regions’ resistances, which is not always true. Also, data preparation is a manual process; engineers seeking a resistance value between two pins must draw each polygon along the polygon path and place the input and output voltage boundary plates on the layout. This manual process is tedious, error-prone, and time consuming.

General Description

The disclosed method receives the following data:

§         A resistor-annotated 2D polygon description of the layout

§         A resistor-based connectivity description of a pin-to-pin path

§         Names of two pins that belong to the connectivity description

§         The process technology information (i.e. layer resistances, layer thicknesses, etc.)

The disclosed method generates a 3D graphical representation of the polygon path between the given pins, including two voltage boundary plates at the location of the two interface pins. In addition, it computes the resistance value of the polygon path between the given pin pair. The disclosed method is comprised of the following two components: (See Flow Chart of Invention i.e. Figure 1 below)

§         Polygon Path Extractor (PPE). The  PPE builds a 3D representation of the polygon path between the two g...