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Circuit Contention Free Scan Testing

IP.com Disclosure Number: IPCOM000033784D
Publication Date: 2004-Dec-28
Document File: 4 page(s) / 32K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables VLSI design circuits with full scan designs to operate contention-free during scan testing, thereby making them automatic test generation program (ATPG) and Logic-BIST friendly. Benefits include improving and simplifying testing.

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Circuit Contention Free Scan Testing

Disclosed is a method that enables VLSI design circuits with full scan designs to operate contention-free during scan testing, thereby making them automatic test generation program (ATPG) and Logic-BIST friendly. Benefits include improving and simplifying testing.

Background

Drivers feeding multi-drop buses and pass-gate multiplexers require that only one bus driver or multiplexer select line is active. Violating this requirement may lead to circuit contention or a floating node. Either of these situations can cause severe damage to circuits. A VLSI circuit implementation sometimes drives bus enables and multiplexer select controls directly from flip-flops. The circuit feeding these flip-flops ensures that only one of the flip-flops is set. This is referred to as “one-hot” control flip-flops.

Circuits involving one-hot flip-flops work well during normal operation, but they violate the one-hot property during scan testing. Full scan designs use all state elements in the circuit, so that during testing the sequential circuit transforms into two parts: a shift register path (called a scan-path) formed by all scan-flops, and the combinational logic left behind. The shift register path is tested by a simple test pattern. The combinational logic is tested by shifting a test vector using the scan-path, then using one or more system clocks to apply the shifted test on the combinational circuits. The circuit is then returned to scan mode, to shift out the captured response vector and shift in the new test vector. The test vectors (i.e. stimuli and response pairs) for such circuits are generated automatically by commonly available ATPG programs.

Unfortunately one-hot flip-flops, implemented as ordinary scan-flops, expose the enables and select lines to the shifting bit pattern, causing circuit conflicts for hundreds and thousands of cycles. There are two additional problems with implementing scan on one-hot flip-flops:

§         The ATPG used for generating test content must be taught about the one-hot property, so that when the shifting ceases, the final content in the control flip-flops is one-hot. Although modern ATPG programs handle such constraints, their performance deteriorates dramatically as the numbers increase.

§         In Logic-BIST, the on-chip hardware supplies pseudo-random test patterns. Although this problem is similar to that faced by ATPG, it is much harder to generate contention-free Logic-BIST patterns. Recently, some hardware-based...