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Electrical Silicon Metal Grid and Decoupling Capacitance Model

IP.com Disclosure Number: IPCOM000033785D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for modeling the metal grid interconnect on silicon fabricated components. The disclosed method provides an electrical representation for simultaneous switching output (SSO) simulations for multiple IO signal path modeling.

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Electrical Silicon Metal Grid and Decoupling Capacitance Model

Disclosed is a method for modeling the metal grid interconnect on silicon fabricated components. The disclosed method provides an electrical representation for simultaneous switching output (SSO) simulations for multiple IO signal path modeling.

Background

As power delivery and SSO behaviors becomes more important, being able to accurately model and predict IO cell performance is crucial. Currently, a single resistor and a single capacitor are used to represent the on-die capacitance and the metal grid interconnect resistance.

General Description

The disclosed method models the metal grid interconnect on silicon fabricated components, and provides an electrical representation of the metal grid to allow SSO simulations for multiple IO signal path modeling. Figure 1 outlines the disclosed method, and shows the following:

§         Condie represents the immediate capacitance on the IO cell.

§         Rondieesr and Condieadj represent the adjacent IO cell capacitance and the metal layer interconnect.

§         Rgrid2bmp and Rbuf2grid represent the metal layer interconnect from bump to grid and grid to buffer, respectively.

§         Rgrid2grid and Rdrvr2drvr connect to the adjacent IO cells.  Figure 1 only shows one connection for power, but user should also connect another pair of resistors on other side of capacitors for ground return path.  This allows accurate power droop and ground bounce modeling under SSO cases.

Advantages

The disclose...