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Routability and Timing Optimization in a Complex Cross-Clock Design

IP.com Disclosure Number: IPCOM000033786D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 55K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that optimizes the cross-clock domain timing paths and the routability of the design, using sets of command codes in the Synopsys constraint file.

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Routability and Timing Optimization in a Complex Cross-Clock Design

Disclosed is a method that optimizes the cross-clock domain timing paths and the routability of the design, using sets of command codes in the Synopsys constraint file.

Background

Currently, VLSI involves complex cross-clock domain designs; the existing Synopsys timing optimizer fails to optimize cross-clock timing violations, making timing closures very difficult. The current state of the art uses automated scripts to analyze all the cross-clock and non-cross-clock timing paths at once, but experiments show that this causes routability problems.

General Description

The disclosed method uses a set of Synopsys command codes in the Synopsys Design Constraint file to optimize the timing and routing on a complex cross-clock domain design.

Note. Before applying the disclosed method, designers must use the Synopsys Astro tool to optimize the placement of all standard cells, and make sure the same clock domain paths are free of timing problems.

The cross-clock domains continue to have timing violations because experiments show that Synopsys Astro tool fails to optimize the cross-clock domain timing violations if the logic cones have very high fan-out (e.g. greater than 9). To continue to fix all timing violations, designers must define a set of Synopsys command codes in the Synopsys Design Constraint (i.e. timing constraint) file as input into Astro. The first set of command codes specifies the same clock domain-ti...