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Predicting Pre-Silicon AC Timing Impacts to an Interface Due to Non-Ideal Powers and Grounds

IP.com Disclosure Number: IPCOM000033787D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for predicting the timing impact to an interface due to the non-ideal powers and grounds in an actual system. Benefits include reducing signal integrity risks on platforms.

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Predicting Pre-Silicon AC Timing Impacts to an Interface Due to Non-Ideal Powers and Grounds

Disclosed is a method for predicting the timing impact to an interface due to the non-ideal powers and grounds in an actual system. Benefits include reducing signal integrity risks on platforms.

Background

Currently, the time valid after(Tva) and time valid before (Tvb) numbers are reported as ideal numbers (i.e. numbers with no power delivery effects considered). The simultaneous switching outputs (SSO) timing impact is accounted for using an arbitrary timing bucket.

Another approach is to measure the Tsu and Thold at the receivers with the non-ideal power delivery network model included in the signal integrity (SI) simulations; however, this approach cannot distinguish between the effects due to the power delivery noise and the effects due to the SI (i.e. transmission line) effects. If this number is used, some of the impacts will be double counted.

General Description

The disclosed method is a simulation methodology for predicting the timing impact to an interface due to the non-ideal powers and grounds in an actual system (see Figure 1). This is best suited for wide interfaces, like system memories, front side buses, or where SSO is an important consideration. The disclosed method consists of setting up a simulation environment that has three parts:

1.      The power delivery network model for the device. This should include the die, package, and mother board implementation of the power network, including all de-coupling capacitors.

2.      All IO buffers on the interface switching in the proper protocol sequence. Each of these IOs must have the proper load and loading topologies (including transmission lines) connected. This entire interface must be connected to the power delivery network mentioned above.

3.      A second set of IOs that connect to the same power delivery network. This second set consists of only one IO buffer per signal type (i.e. one data IO, one CLK IO etc.). Unlike the first set of IOs, these connect only to a spec load. The spec load is the same load that is used to characterize the Tva, Tvb, Tco, and other timing parameters.

Note. All simulations must be run with the full transistor level circuit’s models and the appropriate process files.

Simulations are run without the power delivery network in place (i.e. with ideal power and grounds). The Tva, Tvb, and other timing parameters are measured at the spec loads. These are the ideal Tva and Tvb numbers that have historically been reported by the circuits and apps teams. The same simulation is then run with the power deliv...