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A Phase Gain in Gater Setup Time

IP.com Disclosure Number: IPCOM000033789D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a circuit that enables or disables the clock on the falling edge instead of the rising edge. Benefits include adding a phase of margin and preventing gate leakage.

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A Phase Gain in Gater Setup Time

Disclosed is a method for a circuit that enables or disables the clock on the falling edge instead of the rising edge. Benefits include adding a phase of margin and preventing gate leakage.

Background

Currently, the chopper is used to generate the pre-charge clock for the register file. This circuit is used in places where the pre-charge and evaluation clock are different. The start of pre-charge must be delayed in order to avoid contention. In Figure 1, the falling edge of the node OUT is delayed compared to CLK. Figure 1 also shows the generic clock chopper that generates the pre-charge clock of the domino (i.e. node OUT). The clock gater is used to disable the clock from toggling to save power. In the gater, the enable signal (EN) must be valid before the CLK rises. Figure 2 shows the setup requirements.

General Description

The disclosed method enables or disables the clock on the falling edge instead of the rising edge.

Figure 3 shows the timing diagram of the rising edge enable/disable. The EN disables the rising edge of the clock and produces the signal OUT. The signal OUT remains low until the EN is activated again. The clock then toggles again. This is the conventional clock gating.

Figure 3 also shows the timing diagram of the falling edge enable/disable. The EN is setup to the falling edge of the clock instead of the rising edge of the clock.  This is because the circuitry does not disable the rising edge of the clock, but disables the falling edge of the clo...