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A Non-Clocked Select for Mux Latches

IP.com Disclosure Number: IPCOM000033791D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 20K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a special implementation of the mux that is used to remove clock-gating. Benefits include speeding up the mux performance.

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A Non-Clocked Select for Mux Latches

Disclosed is a method for a special implementation of the mux that is used to remove clock-gating. Benefits include speeding up the mux performance.

Background

Conventional mux latch circuitry is comprised of the standard circuitry with a back-to-back inverter latch (see Figure 1). The select of the mux is clock-gated to make sure that during the hold phase all the selects are turned off; this avoids corrupting the latched data. The clock-gating, however, imposes gate delays, and usually requires an AND gate.

General Description

The disclosed method’s new circuitry is shown in Figure 2.  The circuitry retains data through a feedback loop. The selects of the “second stage” mux (i.e. the four inputs in Figure 2) are always guaranteed mutex, and therefore one of the selects is always active. During the high phase (i.e. transparent phase), the “first stage” muxes always select the data. The mux latch functions as a normal mux when writing data into the latch. During the low phase (i.e. hold phase), the “first stage” muxes select the feedback data from the latch node. This ensures that, no matter which select is active, the latched data is held by the feedback loop.

The advantage of this mux latch is that it can speed up the path coming from the select. The selects no longer need clock-gating, and therefore can avoid stage delay. The disclosed method is also composed of simple static components, so the circuitry can be used by R...