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Spec-Based Repeater Insertion and Cell Placement to Achieve Faster Design Convergence

IP.com Disclosure Number: IPCOM000033793D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 24K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that improves the current state of the art by using a spec that captures the connectivity of a repeated net, and also introduces a cell placement step for maximizing track alignment so that the final solution could accommodate better routing.

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Spec-Based Repeater Insertion and Cell Placement to Achieve Faster Design Convergence

Disclosed is a method that improves the current state of the art by using a spec that captures the connectivity of a repeated net, and also introduces a cell placement step for maximizing track alignment so that the final solution could accommodate better routing.

Background

In high-speed processor designs, effective buffer insertion of interconnect is crucial for achieving block-level timing closures. The traditional methodology first fixes the block placement of a design, and then places repeater regions (i.e. areas specifically used for placing repeater cells) into the chip. An automatic router is used to wire the blocks. Given the fixed placement and routing, the algorithm inserts repeater cells into the best locations inside repeater regions. The algorithm is effective, easy to implement, and also generates optimal solutions. Therefore, this fixed-topology buffer insertion algorithm has been one of the most popular algorithms in the CAD industry.

 

Chip designs require multiple iterations of physical assembly and evaluation loops before convergence is achieved. In order to achieve faster convergence, the repeater solutions generated must remain more or less the same in each reiteration, despite constant changes in the design. A repeater solution contains the regions where repeater cells are needed, and also the detailed placement and type of repeater cells to be used. However, a small change in the design data could potentially produce drastically different routing results. Since the fixed-topology buffer insertion operates on routing, the repeater solution generated could be drastically different from the previous iteration, and therefore the convergence of a design suffers (see Figures 1a and 1b). Figure 2 shows the traditional fixed-topology repeater insertion approach. Furthermore, the current algorithm is sensitive so that small changes in routing could result in big changes in the repeater solution. How to maintain repeater solutions from iteration to iteration remains a fundamental convergence issue in the design community.

General Description

The disclosed method proposes a new flow to maintain repeater solutions. Figure 3 shows the new flow. First, a specification is created that captures the repeater solution. The repeater solution may be obtained from the previous iteration; it might come from user input after extensive...