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On-Die High-Speed Clock and Clock Skew Safety Detector Circuit and Architecture

IP.com Disclosure Number: IPCOM000033794D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 319K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that converts clock oscillation to voltage, to monitor clock functionality and quality. Benefits include acquiring safety observations without disturbing the clock distribution network.

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On-Die High-Speed Clock and Clock Skew Safety Detector Circuit and Architecture

Disclosed is a method that converts clock oscillation to voltage, to monitor clock functionality and quality. Benefits include acquiring safety observations without disturbing the clock distribution network.

Background

In high speed circuit designs, clocking circuitry continues to be a critical block for system functionality and performance. When testing a chip, it is important to know if the clock distribution network functions correctly after fabrication and packaging.

General Description

The disclosed method is composed of an on-die high speed clock detection circuit, as well as a clock skew safety detection circuit and architecture. The disclosed method requires only one extra pin for the clock indicator, and one extra pin for the skew safety indicator. Figure 1 shows the block diagram of the on-die high speed clock detector circuit. The circuit charges the pump to get the clock period information and output a stable voltage which is proportional to the clock unity period. When there is no clock oscillation, the “CLK_Flag” is stuck at zero. The Itest is set either on-chip or off-chip and controlled with other DFT functionalities. From the Itest information and the “CLK_Flag” output voltage, one can observe clock frequency information or tell if clock is dead. The process is as follows:

1.      Set Itest,

2.      In “CLK” high period, the NMOS switch for “CLK” signal is on, and the “CLK_p1” and “CLK_p2” switches are off. Itest charges the left side of the “C” capacitor in the full “CLK” high period. At every beginning of “CLK” high, the left side “C” is already reset to ground, so the “CLK” oscillation charges the left side “C” to the same voltage every “CLK” cycle instead of accumulating cycle to cycle to saturate the left side capacitor “C”

3.      In “CLK” low period, the PMOS switch for the “CLK” signal is on, and Itest is dumped to ground to keep the current biasing the same, as in charging “C” for high speed operation. The NMOS switch for “CLK” signal is off, which keeps the left and right side capacitors “C” isolated from “CLK”

4.      The “CLK_p1” is a short pulse generated from “CLK” with the same frequency. Right after “CLK” goes low, “CLK_p1” goes low, which connects two capacitors on the left and right side of “CLK_p1” switch. Since these two capacitors are of same value, the same voltage is stored on the right side capacitor after many “CLK_p1” low cycles. The voltage representing the “CLK” frequency information is then stored and isolated in the right side capacitor “C” after “CLK_p1” goes back to high. The accuracy is

5.      After “CLK_p1”...