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Method for multiple-bit ECC detection

IP.com Disclosure Number: IPCOM000033805D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 52K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multiple-bit (multi-bit) error correction code (ECC) detection. Benefits include improved functionality and improved reliability.

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Method for multiple-bit ECC detection

Disclosed is a method for multiple-bit (multi-bit) error correction code (ECC) detection. Benefits include improved functionality and improved reliability.

Background

              Conventionally, rotational code protects 64 data bits with 8 check bits. However, this methodology only provides correction and detection for 1-bit errors and detection for 2-bit errors.

              For a basic ECC algorithm, only errors up to 2-bits can be detected. Although even-bit errors alias back as uncorrectable but detectable 2-bit errors, all odd-bit errors alias back as 1-bit corrected errors. The platform could, for example, encounter a 3-bit error and report it as a 1-bit corrected error. In reality, the 3-bit error is uncorrectable and, in this case, undetectable, leading to silent data corruption.

Description

                            The disclosed method provides enhanced coverage to detect all ECC errors. For example Multiple-bit errors alias to either 1-bit for errors of an odd number of bits or 2 bits for errors of an even number of bits.

              The method reports the main memory address of cache lines that are indicated as or aliased to 1xECC. As a result, the original data can be reread and multi-bit errors can be detected. The rereading of the data must occur at a higher architectural level, such as at the platform level if the problem is at the processor level. In-line error correction must be disabled so as not to corrupt the data. If data...