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Method for scatter-gather DMA in chipsets for packet processing applications

IP.com Disclosure Number: IPCOM000033806D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for scatter-gather direct memory access (DMA) in chipsets for packet processing applications. Benefits include improved functionality and improved performance.

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Method for scatter-gather DMA in chipsets for packet processing applications

Disclosed is a method for scatter-gather direct memory access (DMA) in chipsets for packet processing applications. Benefits include improved functionality and improved performance.

Background

              DMA engines in memory controller hub (MCH) components do not support descriptor interleaving and merging, which enable packet composition by the DMA engine instead of by software.

              Two common operations in processing systems include:

•             Moving the received header and data packets to different locations in system memory on the inbound receiving path

•             Fetching the header and data from different memory regions, combining them into a packet, and sending it out on the outbound path

              Conventionally, the CPU prepares combined descriptor lists. They include pointers to headers and data in system memory. DMA engines, which reside in the chipsets or end devices, use these lists to move packets to and from memory. Although multichannel DMAs can handle multiple descriptor lists in parallel, sending combined the header and data in one write is not supported.

Description

              The disclosed method is scatter-gather DMA in chipsets for packet processing applications  (see Figure 1). A single DMA channel interleaves two descriptor lists to fetch header and data from memory. One descriptor list contains addresses to headers. Another contains addresses to data. The CPU ...