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Adaptive Link Width Management Based on Bandwidth and Workload Requirements

IP.com Disclosure Number: IPCOM000033808D
Publication Date: 2004-Dec-28
Document File: 3 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a dynamic and adaptive PCI Express link width management mechanism that is based on bandwidth and workload requirements. Benefits include efficient power and thermal management.

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Adaptive Link Width Management Based on Bandwidth and Workload Requirements

Disclosed is a method for a dynamic and adaptive PCI Express link width management mechanism that is based on bandwidth and workload requirements. Benefits include efficient power and thermal management.

Background

PCI Express devices are composed of the following (see Figure 1):

§         Port. A group of transmitters and receivers (located on the same chip) that define a link

§         Lane. A set of differential signal pairs, one pair for transmission and one pair for reception (with four signals per lane)

§         Link. A dual-simplex communications path between two components (e.g. An XN link is composed of N lanes)

In Figure 1, devices A and B are PCI Express Ports supporting an X1 link. Each X1 link provides a maximum bandwidth of 250Mbytes/sec in each direction (500Mbytes/sec total for Transmit + Receive). On a low power consuming

PCI

Express

Port

, each X1 link involved in the transmission can account for ~200mw of power consumption for both devices involved in the transmission. In a power managed profile it is important to conserve power and maximize battery life usage by scaling the link width from X1 <-> XN, depending on the bandwidth and workload requirements.

General Description

Instead of operating all the XN links between the devices for a low bandwidth usage model, the disclosed method allows for an adaptive link width management strategy dependent on bandwidth and workload to achieve optimal system power consumption. For example, if the workload demands 150Mbytes/sec of bandwidth (which is easily achieved by an X1 link) the other lanes (N-1) between the two PCI express devices are placed into a...