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Improving Thermal Performance of a DRAM Device When Packaged in a Multi-Die Stacked DRAM Package

IP.com Disclosure Number: IPCOM000033809D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 157K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that improves the thermal performance of a DRAM device when packaged in a multi-die stacked DRAM package.

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Improving Thermal Performance of a DRAM Device When Packaged in a Multi-Die Stacked DRAM Package

Disclosed is a method that improves the thermal performance of a DRAM device when packaged in a multi-die stacked DRAM package.

Background

Currently, there is no stacking solution that takes advantage of the unused surfaces of the stacked package for thermal conduction.

General Description

The disclosed method takes advantage of the two edges of  DRAM stacked packages that are not used for the signal interconnect. The DRAM stacked package is extended in the direction of the unused edges to allow for the addition of a plurality of “thermal” solder bumps. The thermal solder bumps are installed in a similar process to the “signal” solder bumps, and enhance the thermal conduction in the z-axis of the DRAM stacked package.  Figure 1 shows a typical stacked package with the signal solder bumps shown on the left and right edges of the stacked package.  Figure 2 shows where the thermal solder bumps are placed in the DRAM stacked package. The signal solder bumps are shown on the left and right edges of the stacked package, and the thermal solder bumps are located on the surfaces coming out and going into the page.

Advantages

The disclosed method takes advantage of the unused dimension in the DRAM stacked package to provide an additional thermal path from the DRAM die to the top and bottom surfaces of the DRAM stacked package.  Heat is conducted from all four sides of the DRAM...