Browse Prior Art Database

Method for ultra-high speed even/odd modulus prescaler with a synchronous redundant state shift register

IP.com Disclosure Number: IPCOM000033811D
Publication Date: 2004-Dec-28
Document File: 2 page(s) / 9K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for ultra-high speed even/odd modulus prescaler with a synchronous redundant state shift register. Benefits include improved functionality, improved performance, and improved power performance.

This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately 54% of the total text.

Method for ultra-high speed even/odd modulus prescaler with a synchronous redundant state shift register

Disclosed is a method for ultra-high speed even/odd modulus prescaler with a synchronous redundant state shift register. Benefits include improved functionality, improved performance, and improved power performance.

Background

              Conventionally, prescalers are designed as a combination of a Johnson Counter, and divide-by-N binary asynchronous ripple counter. Logic is included to switch between the divide by N‑mode and the Johnson-Counter mode to get an N+1 count. The counter state is decoded and fed into the first stage of the Johnson Counter to “swallow” the incoming clock and generate an N+1 count.

Description

              The disclosed method is an ultra-high speed even/odd modulus prescaler with a synchronous redundant state shift register. The prescaler is the key high-frequency circuit element in a fractional N-frequency synthesizer.

              The disclosed method requires no logic to decode the counter state. It functions as a shift register, alternately shifting through strings of logical “1”s and “0”s. The mode-control signal actives the feedback logic to implement the N+1 count. All flip-flops operate synchronously with no intervening levels of logic between the flip-flops, except for the input stage. This design can be further refined to merge this logic into the input stage, to further improve the operating frequency. Changing between 4/5 mode and 8/9 mode is accomplished through multiplexing around the flip-flops not required for the count.

              The disclosed...