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Hierarchical Clock Skew for Timing Analysis

IP.com Disclosure Number: IPCOM000033814D
Publication Date: 2004-Dec-29
Document File: 3 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables general static timing tools to accurately estimate the clock skew and the slack of a design that is partitioned into hierarchies. Benefits include a solution that can be generalized to all timing aspects (i.e. not only to skew) when a design hierarchy is encountered.

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Hierarchical Clock Skew for Timing Analysis

Disclosed is a method that enables general static timing tools to accurately estimate the clock skew and the slack of a design that is partitioned into hierarchies. Benefits include a solution that can be generalized to all timing aspects (i.e. not only to skew) when a design hierarchy is encountered.

Background

With processor designs becoming increasingly complex, hierarchical design methodologies are often mandatory. Currently, when a design is partitioned and a path is crossing a hierarchy, a constant skew value is charged. Choosing the “right” fixed skew during timing analysis is difficult. Charging too much tends to make timing convergence very difficult, while charging too little can significantly increase the risk of a silicon failure.

General Description

The disclosed method enables general static timing tools to accurately estimate the clock skew and the slack of a design that is partitioned into hierarchies. This is done by encoding and decoding the necessary skew factors into the timing black boxes. For a high-performance processor (where a hierarchical design is needed), the disclosed method provides accurate and efficient timing analysis results, and avoids timing escapes.

The disclosed method removes the fixed-skew assumption typically used when the sender and receiver clock paths are part of different hierarchies. The disclosed method has three components: skew modeling, skew encoding, and skew decoding/computing, as shown
in Figure 1.

Skew modeling. Given a clock loop that consists of a sender and a receiver path (see Figure 2), the skew model can be described by the following set of formulae:

 GSS, LSS: global and local statistical skew

 d: distance between local clock buffers (LCBs) of the sender and receiver paths

 NS, NR: total numbers of device stages of the sender and receiver paths 

 tDVS, tDVR: total delay of the sender and receiver paths

 terms: % delay variation due to 1 of misc random or system phenomena

 ETA: scaling factor

: combination of global deterministic skew (GDS) and jitter

 

Many of the paramete...