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Method for a decoder for fast memory access

IP.com Disclosure Number: IPCOM000033849D
Publication Date: 2004-Dec-30
Document File: 8 page(s) / 117K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a decoder for fast memory access. Benefits include improved functionality and improved performance.

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Method for a decoder for fast memory access

Disclosed is a method for a decoder for fast memory access. Benefits include improved functionality and improved performance.

Background

              With high-speed microprocessors, latency must be reduced for cache memory accesses. An address is calculated by adding multiple operands. The result (address) is sent to the cache decoder. The decoder analyzes the address, calculates the correct word line, and initiates the memory access. With the first-level cache getting larger, the address required for a memory access is getting longer and takes longer to generate and decode. At the same time, frequency is getting faster and is increasingly difficult to maintain cache access latency. Reducing the time for address generation and decoding is important.

              In conventional designs, multiple operands are first sent to an adder. This adder is typically some form of a carry-look-ahead adder. The resultant address is stored in cache. A multiple-stage decoder analyzes the address bits and activates one and only one of the many word lines. For example, if a cache is organized so that there are 128 word lines, 4 operands (for example) are added together. A 7-bit address is calculated and sent to cache. A 7-to-128 decoder is used to decode one of 128 word lines.

              Many improvements have been proposed and used to speed up the adder logic or combine some of the logic stages. However, the fundamental concept remains the same. A binary add function is processed as fast as possible. Then a decoder generates a one-hot decoded word line.

One alternative is a redundant-form adder. A PGZ form adder is combined with a special decoder so that the final carry-in information is calculated at the same time the word line is decoded. This form of combined adder-decoder is faster than a simple adding and decoding approach. However, some unique array properties, such as a wide one-hot decoding field, 64/128/256 word lines, and a long wire distribution requirement, are not fully exploited.

              An abacus is an ancient calculator. It uses a special increment/decrement technique along with a divide-and-conquers method to perform additions/subtractions. A number can be represented by increments of 1, 5, 10, 50, 100, 500 and so on. Numbers are broken up into small slices and added together. For example, 167 + 270, the number 167 is first broken up into 100+50+10+5+2 and 270 is broken up into 200 +50+20. All the 100s are added together. At the same time, all the 50s are added together and so on. In the example, the partial-sum is 300+100+30+5+2. An adjustment is made based on the carry 400+30+5+2. The sum is generated by ANDING all the components. In the example, the final result is 400 and 30 and 5 and 2 or 437.

              Similarly, an abacus-style add can be performed instead of a binary add. A binary number can be broken into multiple pieces with each digit incremented by 2 to the power of 0 to the most signif...