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Peer Cycle Support on a PC Platform

IP.com Disclosure Number: IPCOM000033850D
Publication Date: 2004-Dec-30
Document File: 2 page(s) / 29K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a peer pre-decode that uses the existing decoding logic that performs the decoding task which supports both the peer and upstream cycles. Benefits include simplified peer support and improved scalability.

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Peer Cycle Support on a PC Platform

Disclosed is a method for a peer pre-decode that uses the existing decoding logic that performs the decoding task which supports both the peer and upstream cycles. Benefits include simplified peer support and improved scalability.

Background

There is an increasing need for a high-performance internal bus. With the advent of PCI Express, there is an opportunity to design a new scaleable, full-performance backbone that meets today’s needs while providing room for future growth. The PCI Express unidirectional bus and PCI Express transaction layer are designed to separate the upstream and downstream buses (see Figure 1). The upstream and downstream buses are generally called backbone bus.

The downstream bus is a “one-to-many” bus, with one source and many destination devices connected to the backbone. The upstream path is a “many-to-one” bus, with the many source devices on the backbone and the upstream backbone logic at one destination. A peer queue supports the cycle that runs between the devices sitting on the backbone bus. To improve scalability, the downstream bus uses target-based decoding, and the configuration registers reside with the device. This allows the backbone bus to add or remove devices easily. However, this makes it more difficult to run the support peer cycle, because all registers sitting on the backbone bus are scattered; the requesting device does not know if the cycle should go up to the upstream PCI Express port, or should b...