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A System to Modify Flip Chip Package Designs for Shrink Silicon

IP.com Disclosure Number: IPCOM000033863D
Publication Date: 2004-Dec-30
Document File: 4 page(s) / 109K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that modifies the existing flip chip package design so that it accepts the shrink version of the silicon die. Benefits include a faster throughput time.

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A System to Modify Flip Chip Package Designs for Shrink Silicon

Disclosed is a method that modifies the existing flip chip package design so that it accepts the shrink version of the silicon die. Benefits include a faster throughput time.

Background

Currently, shrink designs are made from the original un-shrunk package design layout (see Figure 1). Design features are deleted to make room for the new smaller die. The new die is inserted into the design and all elements that were removed must be recreated manually. The shrink design is then compared to the original un-shrunk design to find any items that were left out or that do not match. This is done to ensure that the performance of the new design is equivalent to the original. Lastly, the design is passed through multiple design checks to verify that the shrink design is able to be manufactured.

General Description

The disclosed method shrinks a portion of the flip chip package design to accommodate a smaller version of the die. Figure 2 shows the overall software process.

In the disclosed method, specific information about the existing die is recorded (e.g. placement, reference designator, die edge, number of die pins, etc.), then the shrink die is placed at the same location as the original die. Using information from both die, the size is calculated as a percentage difference between the two die. All trace segments and vias within the original die edge are moved to a new location, based on the scaling amount; the new v...