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Method for dynamic power efficiency via power-partitioned register files in simultaneous multithreaded architectures

IP.com Disclosure Number: IPCOM000033994D
Publication Date: 2005-Jan-11
Document File: 4 page(s) / 17K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dynamic power efficiency via power partitioned register files in simultaneous multithreaded architectures. Benefits include improved functionality and improved power performance.

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Method for dynamic power efficiency via power-partitioned register files in simultaneous multithreaded architectures

Disclosed is a method for dynamic power efficiency via power partitioned register files in simultaneous multithreaded architectures. Benefits include improved functionality and improved power performance.

Background

              Simultaneous multithreading is a computer architecture capability that enables two or more processing threads to execute on a single processor with very low (near zero) switching processing overhead. Conventionally, this capability is achieved by duplicating the register files that represent most of the executing thread’s architecture state. Active threads are switched by setting a different state file as active. This change does not affect the execution units extensively. They continue to execute using the newly activated architecture state. The previous architecture state remains in offline registers and persists unused until the thread is reactivated.

              A hardware-assisted thread switch can potentially be accomplished within a single instruction cycle. Conventional software thread-switching techniques require expensive thread state save and state restore operations to and from system memory.

              A growing user requirement is power efficiency. One conventional solution is the use of dynamic power modes. It is the capability to selectively power off unused portions of a chip. Special purpose units are powered down when they are not in use. This technique is typically applied to the following units:

•             Serial ports

•             Memory

•             Video accelerators

•             Graphics

•             CPU

              For example, in a cellular phone that has a camera, the camera is not in use most of the time. The imager and image processing logic can be powered down to save the power used in the clock trees and the leakage power.

              Further power gains can be made when a unit must retain information but is inactive. The voltage may be reduced to very low levels or other circuit-based methods may be employed to reduce current leakage.

              Conventional implementations rely on software drivers to sense inactivity and control power. During the time period after activity has stopped until software detects the state and controls the power, the units are dissipating power. Additionally, the units dissipate power during powered up before receiving a workload.

              An alternative solution is a multicore graphics and media architecture that supports simultaneous multithreading in each core. For example, one solution supports as many as 12 simultaneously active threads on each core. To support the required duplication of architecture state for this many simultaneously active threads, up to 10 KB of general purpose registers are closely positioned to each core. When 12 threads are active, the 10 KB register file is partitioned for the 12 threads, yielding ~830 bytes per...