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Method for a noise-rejection selective filter on mission critical signals to meet or exceed system-level ESD test targets

IP.com Disclosure Number: IPCOM000034006D
Publication Date: 2005-Jan-11
Document File: 6 page(s) / 91K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a noise-rejection selective filter on mission critical signals to meet or exceed system-level ESD test targets. Benefits include improved functionality and improved performance.

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Method for a noise-rejection selective filter on mission critical signals to meet or exceed system-level ESD test targets

Disclosed is a method for a noise-rejection selective filter on mission critical signals to meet or exceed system-level ESD test targets. Benefits include improved functionality and improved performance.

Background

      For system-level robustness, computer systems and components must meet system-level electrostatic discharge (ESD) test targets and the European legal ESD limit.

      Although system-level electrostatic discharge (ESD) testing has been conducted for many years, it is gaining in importance. Circuit speed/bandwidth has reached levels where they are responding to an ESD testing gun’s signal frequencies containing the highest energy. Conventionally, engineers rely on the noise reducing solutions typically used and most suited for system-level noise rejection, including the following:

•             Filters

•             Hysteresis

•             Noise blankers

•             Noise blankers with timed hysteresis

      However, none of these solutions provide acceptable immunity for system-level ESD noise.

              Filters are usually either low-pass, high-pass or band-pass. A low-pass filter rejects frequencies higher than its cut-off frequency. A high-pass rejects frequencies lower than its cut-off. A band-pass permits only frequencies within a certain band of frequencies to pass. Depending on the nature of the noise, designs can utilize one or more filters (see Figure 1).

              A sense-amplifier is used at the input and hysteresis is achieved through the use of an output-controlled reference generator. The reference voltage is shifted in a direction opposite to the input signal. For example, it can be equal to Vh+ for a low to high transition (see Figure 2).

              A logic blanking circuit blocks out any noise for some period of time by closing the input path for a fixed amount of delay (see Figure 3).

              The design of a noise rejection receiver can incorporate a logic blanker and timed-hysteresis control to eliminate any false triggering due to input noise (see Figure 4).

              Because these solutions are mainly developed and targeted towards rejecting noise in a given system under normal operating conditions, their response and effectiveness is unpredictable for system-level ESD testing. This situation is partly due to an inability to model the impact of ESD noise in a system-level environment. As a result, unpredictable noise levels in receiver inputs can occur during testing or during real ESD events.

              All computer systems must pass legal and other equipment manufacturer (OEM) requirements that test the electrostatic resiliency of a system in operation. These types of tests shock a given system at voltages of 8 kV and higher with predefined setup and controls to monitor the system’s response. These tests stress the source, the signal path, and the receiver cir...