Browse Prior Art Database

Effecting a One-Cycle Cache Access in a Pipeline Having Split D/A Using Dlo Bandwidth

IP.com Disclosure Number: IPCOM000034042D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

A technique is provided in a machine having a wide transfer path for accomplishing a three-stroke operation for RX-type instructions in a four-stroke pipeline having a one-and-a-half cycle cache fetch. The technique includes: in a first cycle, in parallel with decoding, reading the base register and initiating a line transfer from cache to a DL0 cache; in a second cycle, generating an address and comparing the address to the base register upon resolution of the initiated line transfer; and in a third cycle, executing the compared appropriate doubleword. As seen in Fig. 1, the prior art includes four-stroke pipelines having one-and-a-half cycle cache fetches. Decoding occurs in a first cycle 10, where the instruction format is determined and the appropriate registers are read while decoding completes.

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Effecting a One-Cycle Cache Access in a Pipeline Having Split D/A Using Dlo Bandwidth

A technique is provided in a machine having a wide transfer path for accomplishing a three-stroke operation for RX-type instructions in a four-stroke pipeline having a one-and-a-half cycle cache fetch. The technique includes: in a first cycle, in parallel with decoding, reading the base register and initiating a line transfer from cache to a DL0 cache; in a second cycle, generating an address and comparing the address to the base register upon resolution of the initiated line transfer; and in a third cycle, executing the compared appropriate doubleword. As seen in Fig. 1, the prior art includes four-stroke pipelines having one-and-a-half cycle cache fetches. Decoding occurs in a first cycle 10, where the instruction format is determined and the appropriate registers are read while decoding completes. In a second cycle 30, cache access is completed, and in the fourth cycle 40, the appropriate operation is executed. It has been recognized that for most BDX operands, the index register is not used and the displacement is typically small. Thus, it is frequently the case that the line that contains a desired operand can be inferred from the contents of the base register alone. In machines with wide transfer paths, such as machines having DL0s, the data line can be prefetched during the decode cycle. Thus, as seen in Fig. 2, during a first cycle 50, decoding occurs as the format is de...