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Fast Carry Propagating Cmos Full Adder

IP.com Disclosure Number: IPCOM000034049D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Nicot, S: AUTHOR

Abstract

The circuit described hereafter has been designed to have a rather high carry propagation time when used in a ripple carry adder. A possible way to implement a Full Adder is to map the following equations into circuits with logic functions. - Sum = (A Xor B) Xor Cin - Cout = (A Xor B).Cin + A.B But this solution gives a rather slow carry propagation when the carry has to ripple from one bit to another. In the present approach, the logic tables have been mapped directly into design with transfer gates.

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Fast Carry Propagating Cmos Full Adder

The circuit described hereafter has been designed to have a rather high carry propagation time when used in a ripple carry adder. A possible way to implement a Full Adder is to map the following equations into circuits with logic functions. - Sum = (A Xor B)

Xor Cin - Cout = (A Xor B).Cin + A.B But this solution gives a rather slow carry propagation when the carry has to ripple from one bit to another. In the present approach, the logic tables have been mapped directly into design with transfer gates. A B AxorB Sum Cout

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0 0 0 Cin B

0 1 1 --- Cin

1 0 1 --- Cin

1 1 0 Cin B In order to accelerate the carry propagation two different bits have been designed for even and odd bits. The figure shows the schematic of the even and odd bit carry propagating stage. With this architecture, the path to propagate the carry through 2 bits consists in 2 transfer gates and 2 inverters. So the delay to propagate the carry through 1 bit is the delay due to one transfer gate and one inverter. When this architecture is mixed at bit level with carry look ahead at adder level, very fast adders can be designed.

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