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Central Synchronization Unit for Efficient Chip Testing on the ATE

IP.com Disclosure Number: IPCOM000034123D
Publication Date: 2005-Jan-17
Document File: 3 page(s) / 49K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that includes a central first-in first-out (FIFO) synchronization circuit in the top hierarchy of a chip. This circuit synchronizes all testability signals to the tester clk domain, which serves to clock the read stage of the production FIFO (PFIFO). Benefits include a solution that reduces costs and is simple to implement.

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Central Synchronization Unit for Efficient Chip Testing on the ATE

Disclosed is a method that includes a central first-in first-out (FIFO) synchronization circuit in the top hierarchy of a chip. This circuit synchronizes all testability signals to the tester clk domain, which serves to clock the read stage of the production FIFO (PFIFO). Benefits include a solution that reduces costs and is simple to implement.

Background

After manufacturing, production environment chips are submitted to two test cycles: “Sort” before packaging, and “Class” after packaging but prior to being shipped to customers. The tests are conducted with ATE testers, which inject patterns into the chip inputs and sample the chip outputs. The outputs are sampled and compared to the expected “good” responses of the chip.

This process is conducted for all units, and represents a large portion of the total chip cost. There are four major contributors to the cost of the production test program:

§         Test time

§         Cost of the ATE

§         Complexity of the test program (e.g. time, engineers, etc)

Until recently, all tests were “simple”; the internal chip PLL was bypassed on the ATE, and data was injected with the tester clk and sampled with it. All simple, readily available ATEs operate in this manner; however, these ATEs are not designed for sampling data with the DUT clock. 

Sometimes, when special tests scenarios required it (i.e. at speed tests etc), the test was conducted with an internal PLL, and for each chip the ATE ran a specially developed edge-search routine that established the DUT’s timing; the test was conducted with this acquired timing. However, the penalty was twofold: the development of this routine (using C-code), and having to conduct the test for one chip (when usually 2-4 chips were tested in parallel). In addition, this approach forced the development of phase deterministic PLL’s which prevent the test from running after every reset.

However, the new bus standards being developed (such us PCI-E, SATA, IBA, 802.3 Serdes) are all serial high-speed differential buses that have their clk embedded in the data. This type of standard requires a time recovery mechanism that aligns the clock to the incoming data for correct sampling. The RX path of the chip is therefore clocked by the recovered clock. Older techniques do not work well with this requirement, and are too time consuming.

General Description

The disclosed method uses a central FIFO synchron...