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Chip Substrate Package with Pins as Second-Level Interconnects to Increase Second-Level I/O Count

IP.com Disclosure Number: IPCOM000034128D
Publication Date: 2005-Jan-17
Document File: 3 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses pins as second-level interconnects on both sides of the flip chip substrate package, to increase second-level I/O counts and improve signals and power routing.

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Chip Substrate Package with Pins as Second-Level Interconnects to Increase Second-Level I/O Count

Disclosed is a method that uses pins as second-level interconnects on both sides of the flip chip substrate package, to increase second-level I/O counts and improve signals and power routing.

Background

Currently, there is a limited number of pins on the flip chip pin grid array (FC-PGA) packages (see Figure 1). This is compensated for by reducing the pin pitch, and by using pins with smaller dimensions.

General Description

Figure 2 shows the disclosed method in which the substrate has both secondary-side and die-side pins, as compared to the current state of the art which only has pins on the substrate secondary- side. Figure 3 shows the cross section of the substrate build-up, with the copper traces connecting the substrate bumps to the die-side pins, enabling faster routing of the signal from the die to the mother board through the die-side pins. Figure 4 shows the enabling portion, in which an additional socket on the die-side is connected to the mother board through a flex cable connector.

Advantages

The following are advantages of the disclosed method:

§         The number of pins can be increased, without the need to shrink the pin pitch or use pins with smaller dimensions.

§         Pins on the die-side significantly improve signal routing between die-side and the board.

Fig. 1

Fig. 2

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Fig. 4

Disclosed anonymously