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Vertical Deflection Circuit of Non-Self Oscillation Type

IP.com Disclosure Number: IPCOM000034152D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Kobayashi, M: AUTHOR

Abstract

Disclosed is a vertical deflection circuit of non-self oscillation type. A circuit having hysteresis loop characteristics is connected between a source of vertical synchronizing pulses and a sawtooth wave generator. The circuit has advantages of generating pulses for triggering the sawtooth wave generator in synchronism with a frequency of the vertical synchronizing pulses. Referring to Fig. 1, a reference numeral 1 represents a transistor-transistor logic circuit of an open-collector type of an output stage of a control circuit. The transistor-transistor logic circuit 1 generates vertical synchronizing pulses. A voltage source +B1 and resistors R1 and R2 form a pull-up circuit. A pulled up vertical synchronizing pulse is applied to an inverting input of a comparator circuit 2 as Vin through a resistor R3.

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Vertical Deflection Circuit of Non-Self Oscillation Type

Disclosed is a vertical deflection circuit of non-self oscillation type. A circuit having hysteresis loop characteristics is connected between a source of vertical synchronizing pulses and a sawtooth wave generator. The circuit has advantages of generating pulses for triggering the sawtooth wave generator in synchronism with a frequency of the vertical synchronizing pulses. Referring to Fig. 1, a reference numeral 1 represents a transistor-transistor logic circuit of an open-collector type of an output stage of a control circuit. The transistor- transistor logic circuit 1 generates vertical synchronizing pulses. A voltage source +B1 and resistors R1 and R2 form a pull-up circuit. A pulled up vertical synchronizing pulse is applied to an inverting input of a comparator circuit 2 as Vin through a resistor R3. A bias voltage, the value of which is determined by a voltage source +B2 and resistors R4 and R5, is applied to a non-inverting input of the comparator circuit 2 through a resistor R6. An output Vout of the comparator circuit 2 is applied to a base of a transistor Q1. Resistors R7, R8 and R9 and a Darlington transistor pair Q2 form a feed-back circuit to the non-inverting input of the comparator circuit 2. The Vin-Vout characteristics of the comparator circuit 2 indicates a hysteresis loop, as shown in Fig. 2, which is determined by the characteristics of the comparator circuit 2 and the feed-back circui...