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Self-Aligned Quasi-Semiconductor-On-Insulator CMOS Structure

IP.com Disclosure Number: IPCOM000034169D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Sun, YC: AUTHOR [+2]

Abstract

A technique is described whereby a self-aligned quasi-semiconductor- on-insulator (SOI) CMOS structure is fabricated so as to provide high performance, high density and high immunity to latch up and soft errors. The self-aligned quasi SOI CMOS structure, as shown in the figure, utilizes insulator layers buried underneath the source and drain regions and self-aligned to gate channels, source/drain, and isolation regions of the MOS device. The self-alignment of the buried insulator layers is achieved in the same way as that of the source and drain regions by the gate electrode and the field isolation. The key process step is to implant elemental species after the delineation of the gate electrode, which can later be reacted with the substrate material, to form the buried insulator.

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Self-Aligned Quasi-Semiconductor-On-Insulator CMOS Structure

A technique is described whereby a self-aligned quasi-semiconductor- on-insulator (SOI) CMOS structure is fabricated so as to provide high performance, high density and high immunity to latch up and soft errors. The self-aligned quasi SOI CMOS structure, as shown in the figure, utilizes insulator layers buried underneath the source and drain regions and self-aligned to gate channels, source/drain, and isolation regions of the MOS device. The self-alignment of the buried insulator layers is achieved in the same way as that of the source and drain regions by the gate electrode and the field isolation. The key process step is to implant elemental species after the delineation of the gate electrode, which can later be reacted with the substrate material, to form the buried insulator. For example, oxygen or nitrogen can be implanted into the silicon substrate to form silicon dioxide, or nitride, by subsequent heat treatments. This structure is called a quasi-SOI, since only source/drain diffusion regions are on the insulator. The resulting product provides the following advantages: $ Low capacitance in the diffusion areas.

$ Firm substrate and well biases, eliminating problems

associated with the floating substrate in full SOI.

$ Improved latch up immunity due to reduced emitter areas.

$ Allows borderless contacts against diffusion/isolation

edges.

$ The buried insulator layer can be used to control the

junction depth of the source/drain diffusions.

$ There will be no junction leakage problems at the

diffusion-isolation edge caused by self-aligned

silicidation.

$ The drains of complementary semiconductor devices in an

inverter circuit may be butted together on top of buried

insulator layers without an isolation region in between.

$ Minimum isolation dimensions, lithography limited, can be

allowed since the short channel effect of the parasitic

field device is essentially eliminated.

$ Dense layout of circuits can be provided because of the

improved isolation, latchup immunity, borderless contact

and zero n+/p+ spacings. The fabrication process consists of the follo...