Browse Prior Art Database

Low Cost Multiple Hang Timers

IP.com Disclosure Number: IPCOM000034175D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Bergey, AL: AUTHOR

Abstract

"Hang" timers are very useful error-detecting mechanisms. A free- running timer that interrupts a microprocessor or issues a check condition when it is not reset often enough can detect many classes of hardware or microcode failure. Normally, one counter is required to construct each timer. However, this invention builds multiple timers from a single counter. Thus, it performs a traditional function less expensively than the prior art. This mechanism consists of a single counter and two or more three-state finite state machines - one finite state machine for each timer. The counter is free-running. Every time the counter overflows, all the finite state machines move from their present state to the next state (see Fig. 1).

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Low Cost Multiple Hang Timers

"Hang" timers are very useful error-detecting mechanisms. A free- running timer that interrupts a microprocessor or issues a check condition when it is not reset often enough can detect many classes of hardware or microcode failure. Normally, one counter is required to construct each timer. However, this invention builds multiple timers from a single counter. Thus, it performs a traditional function less expensively than the prior art. This mechanism consists of a single counter and two or more three-state finite state machines - one finite state machine for each timer. The counter is free-running. Every time the counter overflows, all the finite state machines move from their present state to the next state (see Fig. 1). If nothing intervenes, all the finite state machines enter the error state after two consecutive counter overflows. Each microprocessor should reset its timer at least once every counter overflow, to avoid the interrupt or check condition. Resetting the timer forces the associated finite state machine to 00. Unlike conventional hang timers, the timeout period of this timer is variable. The timeout varies from one to two times the period of the counter. If a microprocessor resets its timer just before a counter overflow, then two counter overflows will occur after slightly more than one counter period, and the timer will timeout relatively early. This case is shown in Fig. 2. The hang timer spends almost one full per...