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Method for Improved Stress Testing of Performance in a Processor Using a Two-Phase Clock System

IP.com Disclosure Number: IPCOM000034198D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Dick, CJ: AUTHOR [+4]

Abstract

In a two-phase clocking scheme, the relative timing of the trailing edge of the first clock pulse, with respect to the leading edge of the second clock pulse, determines many of the critical timings in the system. Prior processor designs required a global change of operating frequency to perform stress testing of machine performance. Logic added to an on-chip clock distribution circuit provides the ability to stress the logic paths on a given chip separately from all other chips. Chip-to-chip paths can be stressed independently, with the stress being applied to a grouping of chips in the system. The following implementation illustrates the method. (Image Omitted) Referring to the critical timing diagram which is drawn for a positive active clock signal (Fig.

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Method for Improved Stress Testing of Performance in a Processor Using a Two-Phase Clock System

In a two-phase clocking scheme, the relative timing of the trailing edge of the first clock pulse, with respect to the leading edge of the second clock pulse, determines many of the critical timings in the system. Prior processor designs required a global change of operating frequency to perform stress testing of machine performance. Logic added to an on-chip clock distribution circuit provides the ability to stress the logic paths on a given chip separately from all other chips. Chip-to-chip paths can be stressed independently, with the stress being applied to a grouping of chips in the system. The following implementation illustrates the method.

(Image Omitted)

Referring to the critical timing diagram which is drawn for a positive active clock signal (Fig. 1), the following items can be stated: Cycle time of the machine is defined from the rising edge of the C2 clock to the next rising edge of the C2 clock. The first critical timing is a check for the maximum delay that a path may have. The allowed delay is from the leading (rising) edge of the C2 clock to the trailing (falling) edge of the next C1 clock. This is called the long path limit. The second critical timing is a check to ensure that there is a minimum delay in the path so that a race condition does not exist. In this case, the timing is from the rising edge of the C2 to the falling edge of the C1 in the same cycle. This is called the short path limit. In prior-art machines only the long path limit could be stressed. This stressing was performed by reducing the period or cycle of both clocks, effectively shortening the time from the rise of C2 to fall of C1. This same stress condition can be achieved by introducing a gap between the f...