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Common Data Base Schema for Hierarchical Very Large-Scale Integration Design

IP.com Disclosure Number: IPCOM000034211D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 6 page(s) / 70K

Publishing Venue

IBM

Related People

Cagle, JW: AUTHOR [+5]

Abstract

VLSI (very large-scale integration) design presents storage and design tool problems due to databases that have flat structure and make no provision for representing incremental changes as the design progresses. A method is described which solves these problems with an hierarchical representation containing only pertinent data which may be incrementally specified. VLSI design presents storage and design tool problems due to the large volume of data commonly manipulated. Existing databases, such as Physical Work Files (PWFs), Collection of Indexable Data (CIDs), and Interactive Technology Files (ITFs) of the Engineering Design System (EDS), are satisfactory for up to roughly 20K circuits. Beyond this size their structure and data representation exacerbate the storage problem severely.

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Common Data Base Schema for Hierarchical Very Large-Scale Integration Design

VLSI (very large-scale integration) design presents storage and design tool problems due to databases that have flat structure and make no provision for representing incremental changes as the design progresses. A method is described which solves these problems with an hierarchical representation containing only pertinent data which may be incrementally specified. VLSI design presents storage and design tool problems due to the large volume of data commonly manipulated. Existing databases, such as Physical Work Files (PWFs), Collection of Indexable Data (CIDs), and Interactive Technology Files (ITFs) of the Engineering Design System (EDS), are satisfactory for up to roughly 20K circuits. Beyond this size their structure and data representation exacerbate the storage problem severely. Their flat structure necessitates treating the entire design in one piece. They commonly attempt to store all design data in one file. They require a separate representation of the data for each design phase since only occasional provision is made for null or partially specified data which is updated as the design progresses.

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The method disclosed here to solve the above problems is a database design called CDB (common data base). CDB is a hierarchical and minimal representation of data for the VLSI physical design problem which exploits the benefits of Universal Syntax. CDB features a minimal set of general constructs to specify and document the design. Specification data describes what constraint the design must meet (that a block exists, what side its I/Os fall on). Documentation data describes what the design actually is (a block's location, height, and width or exactly where its I/Os are). These constructs are:

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Construct BLKDEF

A physical design unit such as a chip, macro, or

circuit.

OPEN Available open wiring channels through the block.

POWER Channels blocked by power buses.

PIN Locations, name, level and logical net name of I/O

pins.

PINRPT Defines the repetition of a single logical I/O in

multiple physical locations.

BITDEF Describes sets of channels dedicated to routing

entire data buses of signals - used in describing

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'bit stack' structures.

SWAP Which pins may be legally interchanged.

PLACE Locations of other blocks placed inside this

block.

IMAGE Describes locations of rows of circuits in random

logic blocks.

GRID GL/1 pitch, stepsize, and unit.

STAT Describes summary statistics on nets, pins, etc.

TIMEDATE Most recent update of block.

TRACE Programs which processed the block and their

return

codes. Each of the above constructs is formatted as a statement. A detailed description of each statement type follows. The following benefits are obtained: A. The tops-down orientation inherent in the CDB

schema permits the minimum amount of information

to be stored in the CDB. A given BLKDEF contains

only the data required by th...