Browse Prior Art Database

High-Performance DRAM REFRESH Mechanism

IP.com Disclosure Number: IPCOM000034212D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Shimizu, S: AUTHOR

Abstract

This article describes a new DRAM refresh mechanism to reduce an overhead for DRAM refreshing. In this mechanism, DRAM memory is refreshed in parallel with the usual read or write access. And hence, the overhead for refreshing is reduced to zero in an ordinal condition of memory usage. A DRAM memory must be refreshed periodically to replace the charge which has leaked away. The overhead for refreshing DRAM chips becomes very critical for a large memory system, since a large DRAM array must be divided into several small sub-arrays and those sub-arrays must be refreshed sequentially because of power dissipation. (Image Omitted) The new DRAM refresh mechanism is shown below, using an example for simplicity. A memory system of 16M byte consisting of 128 chips of 1M bit DRAM is used as modules of 32 DRAMs each.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

High-Performance DRAM REFRESH Mechanism

This article describes a new DRAM refresh mechanism to reduce an overhead for DRAM refreshing. In this mechanism, DRAM memory is refreshed in parallel with the usual read or write access. And hence, the overhead for refreshing is reduced to zero in an ordinal condition of memory usage. A DRAM memory must be refreshed periodically to replace the charge which has leaked away. The overhead for refreshing DRAM chips becomes very critical for a large memory system, since a large DRAM array must be divided into several small sub-arrays and those sub-arrays must be refreshed sequentially because of power dissipation.

(Image Omitted)

The new DRAM refresh mechanism is shown below, using an example for simplicity. A memory system of 16M byte consisting of 128 chips of 1M bit DRAM is used as modules of 32 DRAMs each. For the memory system, a 24-bit address is used for specifying the byte address, as shown in Fig. 1. Using the upper 2 bits of the address, one of 4 sub-modules is selected as shown in Fig. 2. Three control signals below and the above address signals are used to access the memory system. . RD (READ): MEMORY READ COMMAND.

. WR (write): memory write command.

. BUSY (busy): specifies that the memory system is busy now. In this article, a DRAM refreshing cycle performed in parallel with the usual read or write access is called as 'implicit refresh', and a DRAM refreshing cycle explicitly required periodically is called as 'explicit refresh'. Some other external master periodically requires 'explicit refresh' by activating RD and WR commands simultaneously. Furthermore, an 11-bit refresh counter C, as shown in Fig. 3 (because 512 rows must be a refresh...