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STATUS Filter Algorithm

IP.com Disclosure Number: IPCOM000034235D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Gedeon, EF: AUTHOR [+2]

Abstract

Using a status filter, to recognize the anomaly of a status byte having valid parity but having an inappropriate combination of status bits for the time of presentation, eliminates certain channel errors which might otherwise hang the channel interface. Channels may hang if presented with inappropriate status. The status filter algorithm detects inappropriate status. If a status byte, received by the channel, has valid parity but is inappropriate, the status filter detects the error to allow for channel recovery. The status filter examines for the following status conditions: Fig. 1 SHORT BUSY SEQUENCE Fig. 2 INITIAL STATUS, NOT COMMAND CHAINING Fig. 3 INITIAL STATUS, COMMAND CHAINING Fig. 4 FIRST STATUS AFTER ZERO INITIAL STATUS Fig.

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STATUS Filter Algorithm

Using a status filter, to recognize the anomaly of a status byte having valid parity but having an inappropriate combination of status bits for the time of presentation, eliminates certain channel errors which might otherwise hang the channel interface. Channels may hang if presented with inappropriate status. The status filter algorithm detects inappropriate status. If a status byte, received by the channel, has valid parity but is inappropriate, the status filter detects the error to allow for channel recovery. The status filter examines for the following status conditions: Fig. 1 SHORT BUSY SEQUENCE Fig. 2 INITIAL STATUS, NOT COMMAND CHAINING

Fig. 3 INITIAL STATUS, COMMAND CHAINING

Fig. 4 FIRST STATUS AFTER ZERO INITIAL STATUS

Fig. 5 FIRST STATUS AFTER CHANNEL END WITHOUT DEVICE END

(Image Omitted)

The status filter will flag valid status if the status is appropriate. If inappropriate status is detected, the status filter flags an interface control check.

Interface control check recovery can then be attempted (see Fig. 6). A representative set of status bits is as follows:

0 = ATTENTION...............(ATN.)

1 = STATUS MODIFIER.........(S.M.)

2 = CONTROL UNIT END........(C.U.E.)

3 = BUSY....................(BSY)

4 = CHANNEL END.............(C.E.)

5 = DEVICE END..............(D.E.)

6 = UNIT CHECK..............(U.C.)

7 = UNIT EXCEPTION..........(U.E.)

INTERFACE CONTROL CHECK.....(IFCC)

(Image Omitted)

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