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PROGRAMMABLE PULSE SEQUENCE CONTROL OF DYNAMIC RAMs

IP.com Disclosure Number: IPCOM000034242D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Brewer, JA: AUTHOR [+3]

Abstract

This article describes a circuit arrangement for generation of accurate and repetitive control and refresh sequences to dynamic random access memory (DRAM) arrays utilizing programmable pulse sequence control. DRAMs are generally cost-effective components to use in any large computer memory system. DRAMs need a large amount of control and sequencing logic to insure that specifications, such as refresh, access time, and precharge, are met. This logic usually involves a clock and its support circuitry, several counters or timers, and a large amount of decode or combinational logic. Frequently, a series of cascaded time delays are also used to guarantee the correct sequencing of the DRAM control lines.

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PROGRAMMABLE PULSE SEQUENCE CONTROL OF DYNAMIC RAMs

This article describes a circuit arrangement for generation of accurate and repetitive control and refresh sequences to dynamic random access memory (DRAM) arrays utilizing programmable pulse sequence control. DRAMs are generally cost-effective components to use in any large computer memory system. DRAMs need a large amount of control and sequencing logic to insure that specifications, such as refresh, access time, and precharge, are met. This logic usually involves a clock and its support circuitry, several counters or timers, and a large amount of decode or combinational logic. Frequently, a series of cascaded time delays are also used to guarantee the correct sequencing of the DRAM control lines.

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In the circuit arrangement disclosed herein, a memory controller is structured around two different sequences of pulses flowing through a multi-tap time delay. The time delay will accept a pulse at its input and then provide that same pulse along its outputs at later known intervals of time. Hence, if a pulse is input to a multi-tap time delay with 20 nanoseconds delay per tap, then the first tap will provide a similar pulse 20 nanoseconds after the input pulse. Similarly, the second tap will provide a pulse 40 nanoseconds after the input, the third tap 60 nanoseconds after the input, and so on. Fig. 1 is a diagram of the circuit, and Fig. 2 is a timing chart for the DRAM controller. A refresh or processor RAM access is used to initiate the first string of pulses through the time delay. This first set of pulses is used to gate the RAM controls row address strobe (RAS), column address strobe (CAS), and row/column select (R/C SEL). The initial pulse also sets...