Browse Prior Art Database

Integrated Service Digital Network Frame Synchronizer

IP.com Disclosure Number: IPCOM000034253D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Gee, TW: AUTHOR [+2]

Abstract

CCITT I.430 defines the characteristics of line signals for Integrated Service Digital Network (ISDN). A logic zero is represented by a 0.75- volt pulse of either plus or minus polarity. A logic one is represented by zero volts. In order to have no net DC voltage on the line, each data zero has a polarity that is opposite from the most recent previous data zero. Clocking is obtained using a phase-locked oscillator running at the bit rate of 192 Kbps. An example of a data stream is shown in Fig. 1. The zeros shown are positive, negative and positive. Framing Bits are grouped together to make a frame 48 bits long. In order to mark the boundaries of frames, a combination of data bits and polarity rule violations is used.

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Integrated Service Digital Network Frame Synchronizer

CCITT I.430 defines the characteristics of line signals for Integrated Service Digital Network (ISDN). A logic zero is represented by a 0.75- volt pulse of either plus or minus polarity.

A logic one is represented by zero volts. In order to have no net DC voltage on the line, each data zero has a polarity that is opposite from the most recent previous data zero. Clocking is obtained using a phase-locked oscillator running at the bit rate of 192 Kbps. An example of a data stream is shown in Fig. 1. The zeros shown are positive, negative and positive. Framing Bits are grouped together to make a frame 48 bits long. In order to mark the boundaries of frames, a combination of data bits and polarity rule violations is used. A polarity violation is defined as a data zero having the same, rather than opposite polarity of the most recent previous data zero. An example of a data stream containing a polarity rule violation is shown in Fig. 2. The data zero marked with * is a code violation.

The following four rules define how frame boundaries are marked: 1. The first bit is a code violated data zero.

2. The second bit is a non-code violated data zero.

3. One and only one code violated data zero is in bits 3-14.

4. No code violations in bits 15-47. One must wait for at least 48 bits to determine if all four conditions are met. Description of Logic to Determine Frame Sync: Referring to the diagram shown in Fig. 3, block #1...