Browse Prior Art Database

Five-Point General-Purpose Register for Microprocessors

IP.com Disclosure Number: IPCOM000034254D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

A technique is described whereby a five-point general-purpose register (GPR) is provided for microprocessors, so as to increase performance, by enabling three read and two write operations to be performed simultaneously. Described are three unique circuits which make up the GPR. . Five-Port Static Random-Access Memory (RAM) Cell A static RAM cell with a p-channel load is used and consists of a cross-coupled CMOS inverter pair and two sets of five word-line pass- transistors, as shown in Fig. 1. The word-line transistors are connected together by means of 'first' metal lines and arranged in a U-shape around p-channel load devices, so as to minimize the cell area. The bit-lines, both true and complement phases, are connected to a sense amplifier through 'second' metal lines to achieve high-speed sensing.

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Five-Point General-Purpose Register for Microprocessors

A technique is described whereby a five-point general-purpose register (GPR) is provided for microprocessors, so as to increase performance, by enabling three read and two write operations to be performed simultaneously. Described are three unique circuits which make up the GPR. . Five-Port Static Random-Access Memory (RAM) Cell A static RAM cell with a p-channel load is used and consists of a cross-coupled CMOS inverter pair and two sets of five word-line pass- transistors, as shown in Fig. 1. The word-line transistors are connected together by means of 'first' metal lines and arranged in a U-shape around p-channel load devices, so as to minimize the cell area. The bit-lines, both true and complement phases, are connected to a sense amplifier through 'second' metal lines to achieve high-speed sensing.

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$ Self-Timed OR Decoder Circuit

Dynamic OR decoders are used, instead of NAND decoders, to achieve high-speed address decoding. Typically, dynamic NAND decoder, for a one-out-of-thirty-two decoding application will use a six-way NAND circuit, as shown in Fig. 2a. However, larger transistors are required, as compared to using a dynamic OR decoder. For an OR decoder, only two transistors in series to ground are used, resulting in a smaller transistor size. Using an OR decoder, as shown in Fig. 2b, can present a minor problem. Instead of performing a one-out-of-thirty-two select, an OR decoder selects thirty-one out of thirty-two. This problem is solved, as shown in Fig. 2c, by gating the outputs of the decoder by means of a self-timed signal (GD), generated from a dummy decoder tree, which decodes a pre-charged (PC) clock signal. The dummy decoder generates its output later than any other decoder trees in the same OR array. By the time the GD signal is generated, thirty-one out of thirty-two decoder trees have discharged their internal nodes, so as to keep their outputs at a high level at node C. Consequently, all thirty-one word- lines are clamped to a low level. The output of each decoder tree is buffered to drive a circuit wire-matrix (WM) which then passes through a 2-way NAND circuit (NAND shutter) to its corresponding word-line driver.

During address decoding, only one out of thirty-two trees will not discharge its internal node. This causes WM to go high, passes through the NAND shutter and finally selects a word-line. Between the five decoders and the NAND shutter array, there is a circuit wire-matrix for the interconnection. The selected word-lines and the circuit wire-matrix are reset to a low level automatically after the memory is accessed. . Self-T...