Browse Prior Art Database

Non-Ohmic Behavior Monitor

IP.com Disclosure Number: IPCOM000034265D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Cottrell, PE: AUTHOR [+2]

Abstract

A semiconductor in-line process monitor is shown which is designed to determine metal-to-silicide and silicide-to-diffusion interface resistance for process parametric control. A silicide and silicon voltage-sensing structure is added to a normal discrete device testing macro. The structure allows the potential difference over both the metal-to-silicide and the silicide-to-silicon interfaces to be measured at varying current levels. This information is used (a) to identify which interface is degrading the transistor characteristics, and (b) to quantify interface resistance as a function of different processes.

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Non-Ohmic Behavior Monitor

A semiconductor in-line process monitor is shown which is designed to determine metal-to-silicide and silicide-to-diffusion interface resistance for process parametric control. A silicide and silicon voltage-sensing structure is added to a normal discrete device testing macro. The structure allows the potential difference over both the metal-to-silicide and the silicide-to-silicon interfaces to be measured at varying current levels. This information is used (a) to identify which interface is degrading the transistor characteristics, and (b) to quantify interface resistance as a function of different processes. Referring to the figure, the field-effect transistor (FET) device formed by Gate B causes current to flow through the first level metal into the silicide-silicon contact CA above the diffusion located in the middle of the structure. Voltage sensing of the silicide (Vsense SILICIDE) is accomplished by introducing a separate non-current- carrying contact X-CA to the diffusion. The voltage sense of the metal (Vsense METAL) follows the scheme of a normal contact resistance monitor and is a separate metal line that connects to + Vdrain at the test structure. Voltage sensing of the silicon requires the FET device formed by Gate A. When the device is turned on, the channel inversion layer connects the line Vsense SILICON to the diffusion in the middle of the structure. Use of the device is crucial in breaking the silicide path between th...