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Enhanced Logic Test System Driver Auto Calibration Algorithm

IP.com Disclosure Number: IPCOM000034268D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Gardner, ML: AUTHOR

Abstract

A new algorithm is shown which results in a reduction in logic test time and enhances tester throughput by automatically calibrating the test system's 1/0 level driver using fewer iterations through the calibration algorithm. A commonly used logic test system's driver auto calibration (DAC) algorithm requires many iterations to achieve a target voltage. Referring to Fig. 1, when a logic test driver is series terminated (usually with a 90-ohm line terminator), good AC characteristics are achieved; however, the applied voltage at the 1 or 0 level DAC does not represent the same voltage seen at the device test pin due to driver offset and a voltage drop across the line terminator.

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Enhanced Logic Test System Driver Auto Calibration Algorithm

A new algorithm is shown which results in a reduction in logic test time and enhances tester throughput by automatically calibrating the test system's 1/0 level driver using fewer iterations through the calibration algorithm. A commonly used logic test system's driver auto calibration (DAC) algorithm requires many iterations to achieve a target voltage. Referring to Fig. 1, when a logic test driver is series terminated (usually with a 90-ohm line terminator), good AC characteristics are achieved; however, the applied voltage at the 1 or 0 level DAC does not represent the same voltage seen at the device test pin due to driver offset and a voltage drop across the line terminator. A common technique used to compensate for the offset and voltage drop is to apply the target voltage at the DAC and measure the actual voltage at the device test pin. The difference in (target - voltage measured) is added to the DAC voltage value through a feedback circuit using the following algorithm:

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NEW PROGRAM VALUE = PRESENT PROGRAM VALUE + (TARGET - PRESENT V-MEAS) By using the old algorithm, five or more iterations are usually required to set the voltage value at the device test pin to within +/- 10 mv. When testing bipolar devices where the input impedance is less than 100 ohms, the number of iterations required to achieve the same precision increases dramatically. Also, the driver offset voltage, device...